diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py
index 37fd3f50b..2eb6b8b70 100644
--- a/litex/build/efinix/ifacewriter.py
+++ b/litex/build/efinix/ifacewriter.py
@@ -201,7 +201,10 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
             cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
 
         for i, clock in enumerate(block["clk_out"]):
-            cmd += 'design.set_property("{}","CLKOUT{}_PHASE","{}","PLL")\n'.format(name, i, clock[2])
+            if block["version"] == "V1_V2":
+                cmd += 'design.set_property("{}","CLKOUT{}_PHASE","{}","PLL")\n'.format(name, i, clock[2])
+            else:
+                cmd += '# Phase shift needs to be implemented for PLL V3\n'
 
         cmd += "target_freq = {\n"
         for i, clock in enumerate(block["clk_out"]):
diff --git a/litex/soc/cores/clock/__init__.py b/litex/soc/cores/clock/__init__.py
index afed6e015..d00518cb5 100644
--- a/litex/soc/cores/clock/__init__.py
+++ b/litex/soc/cores/clock/__init__.py
@@ -16,4 +16,4 @@ from litex.soc.cores.clock.lattice_ecp5  import ECP5PLL
 from litex.soc.cores.clock.lattice_nx    import NXOSCA, NXPLL
 
 # Efinix
-from litex.soc.cores.clock.efinix_trion import TRIONPLL
\ No newline at end of file
+from litex.soc.cores.clock.efinix import TRIONPLL, TITANIUMPLL
diff --git a/litex/soc/cores/clock/efinix_trion.py b/litex/soc/cores/clock/efinix.py
similarity index 93%
rename from litex/soc/cores/clock/efinix_trion.py
rename to litex/soc/cores/clock/efinix.py
index e97294d53..bbb80b933 100644
--- a/litex/soc/cores/clock/efinix_trion.py
+++ b/litex/soc/cores/clock/efinix.py
@@ -16,8 +16,8 @@ class Open(Signal): pass
 # Efinix / TRIONPLL ----------------------------------------------------------------------------------
 
 class TRIONPLL(Module):
-    nclkouts_max = 4
-    def __init__(self, platform, n=0):
+    nclkouts_max = 3
+    def __init__(self, platform, n=0, version="V1_V2"):
         self.logger = logging.getLogger("TRIONPLL")
         self.logger.info("Creating TRIONPLL.".format())
         self.platform   = platform
@@ -33,6 +33,7 @@ class TRIONPLL(Module):
         block["clk_out"] = []
         block["locked"]  = self.name + "_locked"
         block["rstn"]    = self.name + "_rstn"
+        block["version"] = version
         self.platform.toolchain.ifacewriter.blocks.append(block)
 
         # Connect PLL's rstn/locked.
@@ -110,3 +111,11 @@ class TRIONPLL(Module):
 
     def do_finalize(self):
         pass
+
+
+# Efinix / TITANIUMPLL ----------------------------------------------------------------------------------
+
+class TITANIUMPLL(TRIONPLL):
+    nclkouts_max = 5
+    def __init__(self, platform, n=0):
+        TRIONPLL.__init__(self, platform, n, version="V3")