From eb1cd194a17ceb5f751f97a199662238dcd0e682 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 18 Dec 2024 19:19:41 +0000 Subject: [PATCH] treewide: Fix "invalid escape sequence" warnings Exposed with new tests. Signed-off-by: Jiaxun Yang --- litex/soc/cores/cpu/cv32e40p/core.py | 4 ++-- litex/soc/cores/cpu/cv32e41p/core.py | 4 ++-- litex/soc/cores/cpu/cva6/core.py | 4 ++-- litex/soc/cores/cpu/openc906/core.py | 6 +++--- litex/soc/integration/export.py | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/litex/soc/cores/cpu/cv32e40p/core.py b/litex/soc/cores/cpu/cv32e40p/core.py index 682635f40..753c25902 100644 --- a/litex/soc/cores/cpu/cv32e40p/core.py +++ b/litex/soc/cores/cpu/cv32e40p/core.py @@ -65,9 +65,9 @@ def add_manifest_sources(platform, manifest): basedir = get_data_mod("cpu", "cv32e40p").data_location with open(os.path.join(basedir, manifest), 'r') as f: for l in f: - res = re.search('\$\{DESIGN_RTL_DIR\}/(.+)', l) + res = re.search(r'\$\{DESIGN_RTL_DIR\}/(.+)', l) if res and not re.match('//', l): - if re.match('\+incdir\+', l): + if re.match(r'\+incdir\+', l): platform.add_verilog_include_path(os.path.join(basedir, 'rtl', res.group(1))) else: platform.add_source(os.path.join(basedir, 'rtl', res.group(1))) diff --git a/litex/soc/cores/cpu/cv32e41p/core.py b/litex/soc/cores/cpu/cv32e41p/core.py index 13bfa9cff..909c39730 100644 --- a/litex/soc/cores/cpu/cv32e41p/core.py +++ b/litex/soc/cores/cpu/cv32e41p/core.py @@ -64,9 +64,9 @@ def add_manifest_sources(platform, manifest): basedir = get_data_mod("cpu", "cv32e41p").data_location with open(os.path.join(basedir, manifest), 'r') as f: for l in f: - res = re.search('\$\{DESIGN_RTL_DIR\}/(.+)', l) + res = re.search(r'\$\{DESIGN_RTL_DIR\}/(.+)', l) if res and not re.match('//', l): - if re.match('\+incdir\+', l): + if re.match(r'\+incdir\+', l): platform.add_verilog_include_path(os.path.join(basedir, 'rtl', res.group(1))) else: platform.add_source(os.path.join(basedir, 'rtl', res.group(1))) diff --git a/litex/soc/cores/cpu/cva6/core.py b/litex/soc/cores/cpu/cva6/core.py index d69791a63..231bc49c1 100644 --- a/litex/soc/cores/cpu/cva6/core.py +++ b/litex/soc/cores/cpu/cva6/core.py @@ -44,13 +44,13 @@ def add_manifest_sources(platform, manifest): lx_core_dir = os.path.abspath(os.path.dirname(__file__)) with open(os.path.join(manifest), 'r') as f: for l in f: - res = re.search('\$\{(CVA6_REPO_DIR|LX_CVA6_CORE_DIR)\}/(.+)', l) + res = re.search(r'\$\{(CVA6_REPO_DIR|LX_CVA6_CORE_DIR)\}/(.+)', l) if res and not re.match('//', l): if res.group(1) == "LX_CVA6_CORE_DIR": basedir = lx_core_dir else: basedir = cva6_dir - if re.match('\+incdir\+', l): + if re.match(r'\+incdir\+', l): platform.add_verilog_include_path(os.path.join(basedir, res.group(2))) else: filename = res.group(2) diff --git a/litex/soc/cores/cpu/openc906/core.py b/litex/soc/cores/cpu/openc906/core.py index b8144b81b..594f09983 100644 --- a/litex/soc/cores/cpu/openc906/core.py +++ b/litex/soc/cores/cpu/openc906/core.py @@ -61,9 +61,9 @@ def add_manifest_sources(platform, manifest): basedir = os.path.join(os.environ["OPENC906_DIR"], "C906_RTL_FACTORY") with open(os.path.join(basedir, manifest), 'r') as f: for l in f: - res = re.search('\$\{CODE_BASE_PATH\}/(.+)', l) - if res and not re.match('//', l): - if re.match('\+incdir\+', l): + res = re.search(r'\$\{CODE_BASE_PATH\}/(.+)', l) + if res and not re.match(r'//', l): + if re.match(r'\+incdir\+', l): platform.add_verilog_include_path(os.path.join(basedir, res.group(1))) else: platform.add_source(os.path.join(basedir, res.group(1))) diff --git a/litex/soc/integration/export.py b/litex/soc/integration/export.py index 5835e7c22..7d84e0a46 100644 --- a/litex/soc/integration/export.py +++ b/litex/soc/integration/export.py @@ -98,7 +98,7 @@ def get_cpu_mak(cpu, compile_software): for i, l in enumerate(os.popen(selected_triple + "-ar -V")): # Version is last float reported in first line. if i == 0: - version = float(re.findall("\d+\.\d+", l)[-1]) + version = float(re.findall(r"\d+\.\d+", l)[-1]) return version def apply_riscv_zicsr_march_workaround(flags):