From eb64169521b583b032952829de59fbb12c4e426c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 24 Mar 2020 19:36:57 +0100
Subject: [PATCH] build/lattice/diamond: remove ECP3 support. (ECP3 is not used
 and no longer interesting now that ECP5 has an open-source toolchain).

---
 litex/build/lattice/common.py   | 42 ++++++++++++++++-----------------
 litex/build/lattice/diamond.py  |  2 +-
 litex/build/lattice/platform.py |  2 +-
 litex/build/lattice/trellis.py  |  2 +-
 4 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py
index 6c01ac41d..b0a8b4621 100644
--- a/litex/build/lattice/common.py
+++ b/litex/build/lattice/common.py
@@ -9,9 +9,9 @@ from migen.fhdl.bitcontainer import value_bits_sign
 from migen.genlib.io import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-# ECPX AsyncResetSynchronizer ----------------------------------------------------------------------
+# ECP5 AsyncResetSynchronizer ----------------------------------------------------------------------
 
-class LatticeECPXAsyncResetSynchronizerImpl(Module):
+class LatticeECP5AsyncResetSynchronizerImpl(Module):
     def __init__(self, cd, async_reset):
         rst1 = Signal()
         self.specials += [
@@ -28,14 +28,14 @@ class LatticeECPXAsyncResetSynchronizerImpl(Module):
         ]
 
 
-class LatticeECPXAsyncResetSynchronizer:
+class LatticeECP5AsyncResetSynchronizer:
     @staticmethod
     def lower(dr):
-        return LatticeECPXAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
+        return LatticeECP5AsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
 
-# ECPX DDDR Output ---------------------------------------------------------------------------------
+# ECP5 DDDR Output ---------------------------------------------------------------------------------
 
-class LatticeECPXDDROutputImpl(Module):
+class LatticeECP5DDROutputImpl(Module):
     def __init__(self, i1, i2, o, clk):
         self.specials += Instance("ODDRX1F",
             i_SCLK = clk,
@@ -44,21 +44,21 @@ class LatticeECPXDDROutputImpl(Module):
             o_Q    = o,
         )
 
-class LatticeECPXDDROutput:
+class LatticeECP5DDROutput:
     @staticmethod
     def lower(dr):
-        return LatticeECPXDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
+        return LatticeECP5DDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
 
-# ECPX Special Overrides ---------------------------------------------------------------------------
+# ECP5 Special Overrides ---------------------------------------------------------------------------
 
-lattice_ecpx_special_overrides = {
-    AsyncResetSynchronizer: LatticeECPXAsyncResetSynchronizer,
-    DDROutput:              LatticeECPXDDROutput
+lattice_ecp5_special_overrides = {
+    AsyncResetSynchronizer: LatticeECP5AsyncResetSynchronizer,
+    DDROutput:              LatticeECP5DDROutput
 }
 
-# ECPX Trellis Tristate ----------------------------------------------------------------------------
+# ECP5 Trellis Tristate ----------------------------------------------------------------------------
 
-class LatticeECPXTrellisTristateImpl(Module):
+class LatticeECP5TrellisTristateImpl(Module):
     def __init__(self, io, o, oe, i):
         nbits, sign = value_bits_sign(io)
         if nbits == 1:
@@ -84,17 +84,17 @@ class LatticeECPXTrellisTristateImpl(Module):
                 ]
 
 
-class LatticeECPXTrellisTristate(Module):
+class LatticeECP5TrellisTristate(Module):
     @staticmethod
     def lower(dr):
-        return LatticeECPXTrellisTristateImpl(dr.target, dr.o, dr.oe, dr.i)
+        return LatticeECP5TrellisTristateImpl(dr.target, dr.o, dr.oe, dr.i)
 
-# ECPX Trellis Special Overrides -------------------------------------------------------------------
+# ECP5 Trellis Special Overrides -------------------------------------------------------------------
 
-lattice_ecpx_trellis_special_overrides = {
-    AsyncResetSynchronizer: LatticeECPXAsyncResetSynchronizer,
-    Tristate:               LatticeECPXTrellisTristate,
-    DDROutput:              LatticeECPXDDROutput
+lattice_ecp5_trellis_special_overrides = {
+    AsyncResetSynchronizer: LatticeECP5AsyncResetSynchronizer,
+    Tristate:               LatticeECP5TrellisTristate,
+    DDROutput:              LatticeECP5DDROutput
 }
 
 # iCE40 AsyncResetSynchronizer ----------------------------------------------------------------------
diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py
index 083f4ed38..e3f91133f 100644
--- a/litex/build/lattice/diamond.py
+++ b/litex/build/lattice/diamond.py
@@ -146,7 +146,7 @@ class LatticeDiamondToolchain:
         "no_shreg_extract": None
     }
 
-    special_overrides = common.lattice_ecpx_special_overrides
+    special_overrides = common.lattice_ecp5_special_overrides
 
     def __init__(self):
         self.false_paths = set() # FIXME: use it
diff --git a/litex/build/lattice/platform.py b/litex/build/lattice/platform.py
index b4f8593e2..71ff2a653 100644
--- a/litex/build/lattice/platform.py
+++ b/litex/build/lattice/platform.py
@@ -23,7 +23,7 @@ class LatticePlatform(GenericPlatform):
             raise ValueError("Unknown toolchain")
 
     def get_verilog(self, *args, special_overrides=dict(), **kwargs):
-        so = dict()  # No common overrides between ECPX and iCE40.
+        so = dict()  # No common overrides between ECP5 and iCE40.
         so.update(self.toolchain.special_overrides)
         so.update(special_overrides)
         return GenericPlatform.get_verilog(self, *args, special_overrides=so,
diff --git a/litex/build/lattice/trellis.py b/litex/build/lattice/trellis.py
index 066c169c9..154e751dd 100644
--- a/litex/build/lattice/trellis.py
+++ b/litex/build/lattice/trellis.py
@@ -168,7 +168,7 @@ class LatticeTrellisToolchain:
         "no_shreg_extract": None
     }
 
-    special_overrides = common.lattice_ecpx_trellis_special_overrides
+    special_overrides = common.lattice_ecp5_trellis_special_overrides
 
     def __init__(self):
         self.yosys_template   = _yosys_template