From eb688d3af7d611bfb4457bbb2c283f98a71781c6 Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Mon, 9 Jan 2023 16:44:33 +0100 Subject: [PATCH] tools/litex_sim: allow to enable BIST modules Signed-off-by: Michal Sieron --- litex/tools/litex_sim.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 15eabe030..a7cd81605 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -149,6 +149,7 @@ class SimSoC(SoCCore): sdram_data_width = 32, sdram_spd_data = None, sdram_verbosity = 0, + with_bist = False, with_i2c = False, with_sdcard = False, with_spi_flash = False, @@ -195,7 +196,8 @@ class SimSoC(SoCCore): module = sdram_module, l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), - l2_cache_reverse = False + l2_cache_reverse = False, + with_bist = with_bist ) if sdram_init != []: # Skip SDRAM test to avoid corrupting pre-initialized contents. @@ -373,6 +375,7 @@ def sim_args(parser): parser.add_argument("--sdram-init", default=None, help="SDRAM init file (.bin or .json).") parser.add_argument("--sdram-from-spd-dump", default=None, help="Generate SDRAM module based on data from SPD EEPROM dump.") parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity.") + parser.add_argument("--with-bist", action="store_true", help="Enable SDRAM BIST modules.") # Ethernet /Etherbone. parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") @@ -476,6 +479,7 @@ def main(): # SoC ------------------------------------------------------------------------------------------ soc = SimSoC( with_sdram = args.with_sdram, + with_bist = args.with_bist, with_ethernet = args.with_ethernet, ethernet_phy_model = args.ethernet_phy_model, with_etherbone = args.with_etherbone,