From eb9f54b2bca60c416f929acb40c7c5f7db1335d8 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 13 Mar 2020 12:24:36 +0100
Subject: [PATCH] test: add initial (minimal) test for clock abstraction
 modules.

Also fix divclk_divide_range on S6DCM.
---
 litex/soc/cores/clock.py |  2 +-
 test/test_clock.py       | 69 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 test/test_clock.py

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 127eb8336..767659d5d 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -229,7 +229,7 @@ class S6DCM(XilinxClocking):
         self.logger = logging.getLogger("S6DCM")
         self.logger.info("Creating S6DCM, {}.".format(colorer("speedgrade {}".format(speedgrade))))
         XilinxClocking.__init__(self)
-        self.divclk_divide_range = (1, 1) # FIXME
+        self.divclk_divide_range = (1, 2) # FIXME
         self.clkin_freq_range = {
             -1: (0.5e6, 200e6),
             -2: (0.5e6, 333e6),
diff --git a/test/test_clock.py b/test/test_clock.py
new file mode 100644
index 000000000..630d36089
--- /dev/null
+++ b/test/test_clock.py
@@ -0,0 +1,69 @@
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+import unittest
+
+from litex.soc.cores.clock import *
+
+
+class TestClock(unittest.TestCase):
+    # Xilinx / Spartan 6
+    def test_s6pll(self):
+        pll = S6PLL()
+        pll.register_clkin(Signal(), 100e6)
+        for i in range(pll.nclkouts_max):
+            pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
+        pll.compute_config()
+
+    def test_s6dcm(self):
+        dcm = S6DCM()
+        dcm.register_clkin(Signal(), 100e6)
+        for i in range(dcm.nclkouts_max):
+            dcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
+        dcm.compute_config()
+
+    # Xilinx / 7-Series
+    def test_s7pll(self):
+        pll = S7PLL()
+        pll.register_clkin(Signal(), 100e6)
+        for i in range(pll.nclkouts_max):
+            pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
+        pll.compute_config()
+
+    def test_s7mmcm(self):
+        mmcm = S7MMCM()
+        mmcm.register_clkin(Signal(), 100e6)
+        for i in range(mmcm.nclkouts_max):
+            mmcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
+        mmcm.compute_config()
+
+    # Xilinx / Ultrascale
+    def test_uspll(self):
+        pll = USPLL()
+        pll.register_clkin(Signal(), 100e6)
+        for i in range(pll.nclkouts_max):
+            pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
+        pll.compute_config()
+
+    def test_usmmcm(self):
+        mmcm = USMMCM()
+        mmcm.register_clkin(Signal(), 100e6)
+        for i in range(mmcm.nclkouts_max):
+            mmcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
+        mmcm.compute_config()
+
+    # Lattice / iCE40
+    def test_ice40pll(self):
+        pll = USMMCM()
+        pll.register_clkin(Signal(), 100e6)
+        for i in range(pll.nclkouts_max):
+            pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
+        pll.compute_config()
+
+    # Lattice / ECP5
+    def test_ecp5pll(self):
+        pll = ECP5PLL()
+        pll.register_clkin(Signal(), 100e6)
+        for i in range(pll.nclkouts_max):
+            pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
+        pll.compute_config()