diff --git a/litex/__init__.py b/litex/__init__.py
index 2454c0e79..0499e31a8 100644
--- a/litex/__init__.py
+++ b/litex/__init__.py
@@ -1,6 +1,3 @@
-# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages
-__path__ = __import__('pkgutil').extend_path(__path__, __name__)
-
 import sys
 
 # retro-compat 2019-09-30
@@ -12,3 +9,20 @@ from litex.soc.integration import export
 sys.modules["litex.soc.integration.cpu_interface"] = export
 
 from litex.tools.litex_client import RemoteClient
+
+def get_data_mod(data_type, data_name):
+    """Get the pythondata-{}-{} module or raise a useful error message."""
+    imp = "import pythondata_{}_{} as dm".format(data_type, data_name)
+    try:
+        l = {}
+        exec(imp, {}, l)
+        dm = l['dm']
+        return dm
+    except ImportError as e:
+        raise ImportError("""\
+pythondata-{dt}-{dn} module not installed! Unable to use {dn} {dt}.
+{e}
+
+You can install this by running;
+ pip install git+https://github.com/litex-hub/pythondata-{dt}-{dn}.git
+""".format(dt=data_type, dn=data_name, e=e))
diff --git a/litex/data/__init__.py b/litex/data/__init__.py
deleted file mode 100644
index c9b5ae908..000000000
--- a/litex/data/__init__.py
+++ /dev/null
@@ -1,2 +0,0 @@
-# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages
-__path__ = __import__('pkgutil').extend_path(__path__, __name__)
diff --git a/litex/data/find.py b/litex/data/find.py
deleted file mode 100644
index 74c910992..000000000
--- a/litex/data/find.py
+++ /dev/null
@@ -1,15 +0,0 @@
-def find_data(data_type, data_name):
-    imp = "from litex.data.{} import {} as dm".format(data_type, data_name)
-    try:
-        l = {}
-        exec(imp, {}, l)
-        dm = l['dm']
-        return dm.data_location
-    except ImportError as e:
-        raise ImportError("""\
-litex-data-{dt}-{dn} module not installed! Unable to use {dn} {dt}.
-{e}
-
-You can install this by running;
- pip install git+https://github.com/litex-hub/litex-data-{dt}-{dn}.git
-""".format(dt=data_type, dn=data_name, e=e))
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index e55e6252b..9f61c6c69 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -32,7 +32,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
@@ -116,7 +116,8 @@ class BlackParrotRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
-        filename = os.path.join(find_data("cpu", "blackparrot"), "flist_litex.verilator")
+        filename = get_data_mod("cpu", "blackparrot").data_file(
+            "flist_litex.verilator")
         with open(filename) as openfileobject:
             for line in openfileobject:
                 temp = line
diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 75e7ba8cb..ffa910d01 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -9,7 +9,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -97,7 +97,7 @@ class LM32(CPU):
 
     @staticmethod
     def add_sources(platform, variant):
-        vdir = find_data("cpu", "lm32")
+        vdir = get_data_mod("cpu", "lm32").data_location
         platform.add_sources(os.path.join(vdir, "rtl"),
             "lm32_cpu.v",
             "lm32_instruction_unit.v",
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index aa00ee172..d918d8b13 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -6,7 +6,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -99,7 +99,9 @@ class Microwatt(CPU):
 
     @staticmethod
     def add_sources(platform):
-        sdir = os.path.join(find_data("cpu", "microwatt"), "sources")
+        sdir = os.path.join(
+            get_data_mod("cpu", "microwatt").data_location,
+            "sources")
         platform.add_sources(sdir,
             # Common / Types / Helpers
             "decode_types.vhdl",
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index a380e3faf..7c3d86a9b 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -8,7 +8,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -174,7 +174,8 @@ class MOR1KX(CPU):
     @staticmethod
     def add_sources(platform):
         vdir = os.path.join(
-            find_data("cpu", "mor1kx"), "rtl", "verilog")
+            get_data_mod("cpu", "mor1kx").data_location,
+            "rtl", "verilog")
         platform.add_source_dir(vdir)
         platform.add_verilog_include_path(vdir)
 
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 47017ac6b..b798e9dd7 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -180,7 +180,7 @@ class PicoRV32(CPU):
 
     @staticmethod
     def add_sources(platform):
-        vdir = find_data("cpu", "picorv32")
+        vdir = get_data_mod("cpu", "picorv32").data_location
         platform.add_source(os.path.join(vdir, "picorv32.v"))
 
     def do_finalize(self):
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index dff3fe707..c29a2796b 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -33,7 +33,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
@@ -239,7 +239,7 @@ class RocketRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
-        vdir = find_data("cpu", "rocket")
+        vdir = get_data_mod("cpu", "rocket").data_location
         platform.add_sources(
             os.path.join(vdir, "generated-src"),
             CPU_VARIANTS[variant] + ".v",
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 42328d199..157b948a3 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -12,7 +12,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.cpu import CPU
@@ -247,7 +247,7 @@ class VexRiscv(CPU, AutoCSR):
     @staticmethod
     def add_sources(platform, variant="standard"):
         cpu_filename = CPU_VARIANTS[variant] + ".v"
-        vdir = find_data("cpu", "vexriscv")
+        vdir = get_data_mod("cpu", "vexriscv").data_location
         platform.add_source(os.path.join(vdir, cpu_filename))
 
     def use_external_variant(self, variant_filename):
diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index 80cc3753a..745eb75e9 100644
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -14,8 +14,8 @@ import subprocess
 import struct
 import shutil
 
+from litex import get_data_mod
 from litex.build.tools import write_to_file
-from litex.data.find import find_data
 from litex.soc.integration import export, soc_core
 
 __all__ = ["soc_software_packages", "soc_directory",
@@ -102,7 +102,8 @@ class Builder:
             for k, v in exec_profiles.items():
                 define(k, v)
             define(
-                "COMPILER_RT_DIRECTORY", find_data("software", "compiler_rt"))
+                "COMPILER_RT_DIRECTORY",
+                get_data_mod("software", "compiler_rt").data_location)
             define("SOC_DIRECTORY", soc_directory)
             variables_contents.append("export BUILDINC_DIRECTORY\n")
             define("BUILDINC_DIRECTORY", self.include_dir)
diff --git a/litex_setup.py b/litex_setup.py
index be9c3b432..82259f1a1 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -19,7 +19,7 @@ repos = [
     ("migen",        ("https://github.com/m-labs/",        True,  True)),
 
     # LiteX SoC builder
-    ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-software-compiler_rt", ("https://github.com/litex-hub/", False, True)),
     ("litex",        ("https://github.com/enjoy-digital/", False,  True)),
 
     # LiteX cores ecosystem
@@ -38,14 +38,14 @@ repos = [
     ("litex-boards", ("https://github.com/litex-hub/",     False, True)),
 
     # Optional LiteX data
-    ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
 ]
 repos = OrderedDict(repos)
 
diff --git a/setup.py b/setup.py
index 9c7444270..496c65d64 100755
--- a/setup.py
+++ b/setup.py
@@ -17,7 +17,7 @@ setup(
     install_requires=[
         "migen",
         "pyserial",
-        "litex-data-software-compiler_rt",
+        "pythondata-software-compiler_rt",
     ],
     packages=find_packages(exclude=("test*", "sim*", "doc*")),
     include_package_data=True,