From ebe22ca2b6b863ff6d8f17968ec3beb3759a6045 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Wed, 11 Aug 2021 14:12:15 +0200 Subject: [PATCH] =?UTF-8?q?cores/vexriscv=5Fsmp:=20Fix=20vexriscv=5Fsmp?= =?UTF-8?q?=C2=A0doesn't=20build=20without=20a=20memory=20bus?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current code only works with a memory bus because otherwise "generate_cluster_name" doesn't get called. Cluster_name is only needed in the finalize phase. Therefore, the name will now be generated just before its usage. Verifiable with:  litex_sim --cpu-type vexriscv_smp (should be broken before this commit) --- litex/soc/cores/cpu/vexriscv_smp/core.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) mode change 100644 => 100755 litex/soc/cores/cpu/vexriscv_smp/core.py diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py old mode 100644 new mode 100755 index f7c837121..44deb4ee4 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -419,8 +419,6 @@ class VexRiscvSMP(CPU): def add_memory_buses(self, address_width, data_width): VexRiscvSMP.litedram_width = data_width - VexRiscvSMP.generate_cluster_name() - from litedram.common import LiteDRAMNativePort if(not VexRiscvSMP.wishbone_memory): ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width) @@ -457,6 +455,7 @@ class VexRiscvSMP(CPU): def do_finalize(self): assert hasattr(self, "reset_address") + VexRiscvSMP.generate_cluster_name() self.specials += Instance(self.cluster_name, **self.cpu_params) # Add Verilog sources