From ecbd40284a0c1d56c95cc1c13886847549365f2b Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:31:23 +1000 Subject: [PATCH] soc: Don't update CSR alignment when there is no CPU The alignment specified by the standalone core config should be honored. Signed-off-by: Benjamin Herrenschmidt --- litex/soc/integration/soc.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 55bedb629..651f450d7 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -781,7 +781,13 @@ class SoC(Module): for n, (origin, size) in enumerate(self.cpu.io_regions.items()): self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False)) self.mem_map.update(self.cpu.mem_map) # FIXME - self.csr.update_alignment(self.cpu.data_width) + + # We don't want the CSR alignemnt reduced from 64-bit to 32-bit on + # a standalone system with a 64-bit WB and no CPU. + # Should we instead only update alignment if the CPU is *bigger* + # than the CSR ? + if name != "None": + self.csr.update_alignment(self.cpu.data_width) # Add Bus Masters/CSR/IRQs if not isinstance(self.cpu, cpu.CPUNone): if reset_address is None: