From ecd0f0e5486ee542d1aca96ec4082f6443394f3e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 22 Jul 2024 14:24:34 +0200 Subject: [PATCH] cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K. --- litex/soc/cores/ram/lattice_nx.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/ram/lattice_nx.py b/litex/soc/cores/ram/lattice_nx.py index 20eada5da..4eab1172d 100644 --- a/litex/soc/cores/ram/lattice_nx.py +++ b/litex/soc/cores/ram/lattice_nx.py @@ -79,10 +79,10 @@ class NXLRAM(LiteXModule): wren = Signal() self.comb += [ datain.eq(self.bus.dat_w[32*w:32*(w+1)]), - self.bus.dat_r[32*w:32*(w+1)].eq(dataout), If(self.bus.adr[14:14+self.depth_cascading.bit_length()] == d, cs.eq(1), - wren.eq(self.bus.we & self.bus.stb & self.bus.cyc) + wren.eq(self.bus.we & self.bus.stb & self.bus.cyc), + self.bus.dat_r[32*w:32*(w+1)].eq(dataout), ), ] lram_block = Instance("SP512K",