From ecdc4101b410b7e89ec54d428f5196e078bd5f08 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 24 Sep 2015 16:01:08 +0800
Subject: [PATCH] lasmicon: enable refresh at all times

---
 misoc/cores/lasmicon/core.py      |   6 +-
 misoc/cores/lasmicon/refresher.py | 103 +++++++++++++++---------------
 2 files changed, 53 insertions(+), 56 deletions(-)

diff --git a/misoc/cores/lasmicon/core.py b/misoc/cores/lasmicon/core.py
index e06a167d7..c485e96f7 100644
--- a/misoc/cores/lasmicon/core.py
+++ b/misoc/cores/lasmicon/core.py
@@ -12,8 +12,7 @@ class LASMIconSettings:
             read_time=32, write_time=16,
             l2_size=8192,
             with_bandwidth=False,
-            with_memtest=False,
-            with_refresh=True):
+            with_memtest=False):
         self.req_queue_size = req_queue_size
         self.read_time = read_time
         self.write_time = write_time
@@ -23,7 +22,6 @@ class LASMIconSettings:
         else:
             self.with_bandwidth = with_bandwidth
         self.with_memtest = with_memtest
-        self.with_refresh = with_refresh
 
 
 class LASMIcon(Module):
@@ -50,7 +48,7 @@ class LASMIcon(Module):
         ###
 
         self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
-            timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC, enabled=controller_settings.with_refresh)
+            timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
         self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
                 getattr(self.lasmic, "bank"+str(i)))
             for i in range(2**geom_settings.bankbits)]
diff --git a/misoc/cores/lasmicon/refresher.py b/misoc/cores/lasmicon/refresher.py
index 8af685fc0..9cd5e8703 100644
--- a/misoc/cores/lasmicon/refresher.py
+++ b/misoc/cores/lasmicon/refresher.py
@@ -6,65 +6,64 @@ from misoc.mem.sdram.core.lasmicon.multiplexer import *
 
 
 class Refresher(Module):
-    def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True):
+    def __init__(self, a, ba, tRP, tREFI, tRFC):
         self.req = Signal()
         self.ack = Signal()  # 1st command 1 cycle after assertion of ack
         self.cmd = CommandRequest(a, ba)
 
         ###
 
-        if enabled:
-            # Refresh sequence generator:
-            # PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
-            seq_start = Signal()
-            seq_done = Signal()
-            self.sync += [
-                self.cmd.a.eq(2**10),
-                self.cmd.ba.eq(0),
-                self.cmd.cas_n.eq(1),
-                self.cmd.ras_n.eq(1),
-                self.cmd.we_n.eq(1),
-                seq_done.eq(0)
-            ]
-            self.sync += timeline(seq_start, [
-                (1, [
-                    self.cmd.ras_n.eq(0),
-                    self.cmd.we_n.eq(0)
-                ]),
-                (1+tRP, [
-                    self.cmd.cas_n.eq(0),
-                    self.cmd.ras_n.eq(0)
-                ]),
-                (1+tRP+tRFC, [
-                    seq_done.eq(1)
-                ])
+        # Refresh sequence generator:
+        # PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
+        seq_start = Signal()
+        seq_done = Signal()
+        self.sync += [
+            self.cmd.a.eq(2**10),
+            self.cmd.ba.eq(0),
+            self.cmd.cas_n.eq(1),
+            self.cmd.ras_n.eq(1),
+            self.cmd.we_n.eq(1),
+            seq_done.eq(0)
+        ]
+        self.sync += timeline(seq_start, [
+            (1, [
+                self.cmd.ras_n.eq(0),
+                self.cmd.we_n.eq(0)
+            ]),
+            (1+tRP, [
+                self.cmd.cas_n.eq(0),
+                self.cmd.ras_n.eq(0)
+            ]),
+            (1+tRP+tRFC, [
+                seq_done.eq(1)
             ])
+        ])
 
-            # Periodic refresh counter
-            counter = Signal(max=tREFI)
-            start = Signal()
-            self.sync += [
-                start.eq(0),
-                If(counter == 0,
-                    start.eq(1),
-                    counter.eq(tREFI - 1)
-                ).Else(
-                    counter.eq(counter - 1)
-                )
-            ]
+        # Periodic refresh counter
+        counter = Signal(max=tREFI)
+        start = Signal()
+        self.sync += [
+            start.eq(0),
+            If(counter == 0,
+                start.eq(1),
+                counter.eq(tREFI - 1)
+            ).Else(
+                counter.eq(counter - 1)
+            )
+        ]
 
-            # Control FSM
-            fsm = FSM()
-            self.submodules += fsm
-            fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
-            fsm.act("WAIT_GRANT",
-                self.req.eq(1),
-                If(self.ack,
-                    seq_start.eq(1),
-                    NextState("WAIT_SEQ")
-                )
-            )
-            fsm.act("WAIT_SEQ",
-                self.req.eq(1),
-                If(seq_done, NextState("IDLE"))
+        # Control FSM
+        fsm = FSM()
+        self.submodules += fsm
+        fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
+        fsm.act("WAIT_GRANT",
+            self.req.eq(1),
+            If(self.ack,
+                seq_start.eq(1),
+                NextState("WAIT_SEQ")
             )
+        )
+        fsm.act("WAIT_SEQ",
+            self.req.eq(1),
+            If(seq_done, NextState("IDLE"))
+        )