From ece90059493f820b0a3a6693d1df9e7b869f4a8d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 9 Mar 2021 09:07:32 +0100 Subject: [PATCH] cpu/vexriscv/core: Rename timer_enabled parameter to with_timer (for consistency with codebase) and disable timer by default (since increasing resources and causing issue on some iCE40 designs). --- litex/soc/cores/cpu/vexriscv/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 523a4dca9..fa6095c45 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -111,7 +111,7 @@ class VexRiscv(CPU, AutoCSR): flags += " -D__vexriscv__" return flags - def __init__(self, platform, variant="standard", timer_enabled=True): + def __init__(self, platform, variant="standard", with_timer=False): self.platform = platform self.variant = variant self.human_name = CPU_VARIANTS.get(variant, "VexRiscv") @@ -158,7 +158,7 @@ class VexRiscv(CPU, AutoCSR): i_dBusWishbone_ERR = dbus.err ) - if timer_enabled: + if with_timer: self.add_timer() if "debug" in variant: