From ed2578799ba0c6211849dafa182b9f727a580566 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 27 Feb 2019 22:24:56 +0100 Subject: [PATCH] test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) --- litex/soc/interconnect/axi_lite.py | 98 --------------------------- test/test_axi_lite.py | 104 +++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 98 deletions(-) create mode 100644 test/test_axi_lite.py diff --git a/litex/soc/interconnect/axi_lite.py b/litex/soc/interconnect/axi_lite.py index 27c45fde2..a237b8579 100644 --- a/litex/soc/interconnect/axi_lite.py +++ b/litex/soc/interconnect/axi_lite.py @@ -178,101 +178,3 @@ class AXILite2CSR(Module): NextState('IDLE'), ) ) - - -from migen.sim import run_simulation -from litex.soc.interconnect import csr, csr_bus - -def test_axilite2csr(): - class CSRHolder(Module, csr.AutoCSR): - def __init__(self): - self.foo = csr.CSRStorage(32, reset=1) - self.bar = csr.CSRStorage(32, reset=1) - - class Fixture(Module): - def __init__(self): - self.csr = csr_bus.Interface(data_width=32, address_width=12) - self.axi = Interface(data_width=32, address_width=14) - self.submodules.holder = CSRHolder() - self.submodules.dut = AXILite2CSR(self.axi, self.csr) - self.submodules.csrbankarray = csr_bus.CSRBankArray( - self, self.map_csr, data_width=32, address_width=12) - self.submodules.csrcon = csr_bus.Interconnect( - self.csr, self.csrbankarray.get_buses()) - - def map_csr(self, name, memory): - return { - 'holder': 0, - }[name] - - def testbench_write_read(dut): - axi = dut.axi - - for _ in range(8): - yield - - # Write test - yield axi.aw.valid.eq(1) - yield axi.aw.addr.eq(4) - yield axi.w.valid.eq(1) - yield axi.b.ready.eq(1) - yield axi.w.data.eq(0x2137) - - while (yield axi.aw.ready) != 1: - yield - while (yield axi.w.ready) != 1: - yield - yield axi.aw.valid.eq(0) - yield axi.w.valid.eq(0) - - for _ in range(8): - yield - - # Read test - yield axi.ar.valid.eq(1) - yield axi.r.ready.eq(1) - yield axi.ar.addr.eq(4) - - while (yield axi.ar.ready != 1): - yield - yield axi.ar.valid.eq(0) - while (yield axi.r.valid != 1): - yield - yield axi.r.ready.eq(0) - - read = yield axi.r.data - assert read == 0x2137 - - for _ in range(8): - yield - - def testbench_simultaneous(dut): - axi = dut.axi - - for _ in range(8): - yield - - # Write - yield axi.aw.valid.eq(1) - yield axi.aw.addr.eq(2) - yield axi.w.valid.eq(1) - yield axi.b.ready.eq(1) - yield axi.w.data.eq(0x2137) - # Read - yield axi.ar.valid.eq(1) - yield axi.r.ready.eq(1) - yield axi.ar.addr.eq(2) - - yield - yield - - is_reading = yield axi.ar.ready - is_writing = yield axi.aw.ready - - assert is_reading - assert not is_writing - - fixture = Fixture() - run_simulation(fixture, testbench_write_read(fixture.dut), vcd_name='axi-write-read.vcd') - fixture = Fixture() - run_simulation(fixture, testbench_simultaneous(fixture.dut), vcd_name='axi-simultaneous.vcd') diff --git a/test/test_axi_lite.py b/test/test_axi_lite.py new file mode 100644 index 000000000..c350e6488 --- /dev/null +++ b/test/test_axi_lite.py @@ -0,0 +1,104 @@ +import unittest + +from migen import * + +from litex.soc.interconnect import csr +from litex.soc.interconnect import csr_bus +from litex.soc.interconnect import axi_lite + +class CSRModule(Module, csr.AutoCSR): + def __init__(self): + self.foo = csr.CSRStorage(32, reset=1) + self.bar = csr.CSRStorage(32, reset=1) + + +class AXILiteDUT(Module): + def __init__(self): + self.csr = csr_bus.Interface(data_width=32, address_width=12) + self.axi = axi_lite.Interface(data_width=32, address_width=14) + self.submodules.csrmodule = CSRModule() + self.submodules.dut = axi_lite.AXILite2CSR(self.axi, self.csr) + self.submodules.csrbankarray = csr_bus.CSRBankArray( + self, self.map_csr, data_width=32, address_width=12) + self.submodules.csrcon = csr_bus.Interconnect( + self.csr, self.csrbankarray.get_buses()) + + def map_csr(self, name, memory): + return {"csrmodule": 0}[name] + + +class TestAXILite(unittest.TestCase): + def test_write_read(self): + def generator(dut): + axi = dut.axi + + for _ in range(8): + yield + + # Write test + yield axi.aw.valid.eq(1) + yield axi.aw.addr.eq(4) + yield axi.w.valid.eq(1) + yield axi.b.ready.eq(1) + yield axi.w.data.eq(0x2137) + + while (yield axi.aw.ready) != 1: + yield + while (yield axi.w.ready) != 1: + yield + yield axi.aw.valid.eq(0) + yield axi.w.valid.eq(0) + + for _ in range(8): + yield + + # Read test + yield axi.ar.valid.eq(1) + yield axi.r.ready.eq(1) + yield axi.ar.addr.eq(4) + + while (yield axi.ar.ready != 1): + yield + yield axi.ar.valid.eq(0) + while (yield axi.r.valid != 1): + yield + yield axi.r.ready.eq(0) + + read = yield axi.r.data + assert read == 0x2137 + + for _ in range(8): + yield + dut = AXILiteDUT() + run_simulation(dut, generator(dut.dut), vcd_name='axi-write-read.vcd') + + def test_simultaneous(dut): + def generator(dut): + axi = dut.axi + + for _ in range(8): + yield + + # Write + yield axi.aw.valid.eq(1) + yield axi.aw.addr.eq(2) + yield axi.w.valid.eq(1) + yield axi.b.ready.eq(1) + yield axi.w.data.eq(0x2137) + # Read + yield axi.ar.valid.eq(1) + yield axi.r.ready.eq(1) + yield axi.ar.addr.eq(2) + + yield + yield + + is_reading = yield axi.ar.ready + is_writing = yield axi.aw.ready + + assert is_reading + assert not is_writing + + + dut = AXILiteDUT() + run_simulation(dut, generator(dut.dut), vcd_name='axi-simultaneous.vcd')