From ed5746a1fe959306bcfa5652eb60ea9a0eb1dd9a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 22 Mar 2015 10:56:29 +0100 Subject: [PATCH] liteusb: fix imports --- misoclib/com/liteusb/core/__init__.py | 8 ++++---- misoclib/com/liteusb/core/com.py | 10 +++++----- misoclib/com/liteusb/core/crc.py | 3 +-- misoclib/com/liteusb/core/depacketizer.py | 2 +- misoclib/com/liteusb/core/packetizer.py | 2 +- misoclib/com/liteusb/frontend/crossbar.py | 2 +- misoclib/com/liteusb/frontend/dma.py | 2 +- misoclib/com/liteusb/frontend/uart.py | 2 +- 8 files changed, 15 insertions(+), 16 deletions(-) diff --git a/misoclib/com/liteusb/core/__init__.py b/misoclib/com/liteusb/core/__init__.py index a382591ce..42b2ee4b2 100644 --- a/misoclib/com/liteusb/core/__init__.py +++ b/misoclib/com/liteusb/core/__init__.py @@ -1,4 +1,4 @@ -from liteusb.ftdi.uart import FtdiUART -from liteusb.ftdi.dma import FtdiDMA -from liteusb.ftdi.com import FtdiCom -from liteusb.ftdi.crc import FtdiCRC32 \ No newline at end of file +from misoclib.com.liteusb.frontend.uart import FtdiUART +from misoclib.com.liteusb.frontend.dma import FtdiDMA +from misoclib.com.liteusb.core.com import FtdiCom +from misoclib.com.liteusb.core.crc import FtdiCRC32 diff --git a/misoclib/com/liteusb/core/com.py b/misoclib/com/liteusb/core/com.py index 86e49099a..e016638a8 100644 --- a/misoclib/com/liteusb/core/com.py +++ b/misoclib/com/liteusb/core/com.py @@ -1,11 +1,11 @@ from migen.fhdl.std import * from migen.flow.actor import * -from liteusb.ftdi.std import * -from liteusb.ftdi.crossbar import FtdiCrossbar -from liteusb.ftdi.packetizer import FtdiPacketizer -from liteusb.ftdi.depacketizer import FtdiDepacketizer -from liteusb.ftdi.phy import FtdiPHY +from misoclib.com.liteusb.common import * +from misoclib.com.liteusb.frontend.crossbar import FtdiCrossbar +from misoclib.com.liteusb.core.packetizer import FtdiPacketizer +from misoclib.com.liteusb.core.depacketizer import FtdiDepacketizer +from misoclib.com.liteusb.phy.ft2232h import FtdiPHY class FtdiCom(Module): def __init__(self, pads, *ports): diff --git a/misoclib/com/liteusb/core/crc.py b/misoclib/com/liteusb/core/crc.py index df34837c9..26fb76074 100644 --- a/misoclib/com/liteusb/core/crc.py +++ b/misoclib/com/liteusb/core/crc.py @@ -1,4 +1,3 @@ - from collections import OrderedDict from migen.fhdl.std import * from migen.genlib.fsm import FSM, NextState @@ -7,7 +6,7 @@ from migen.genlib.misc import chooser, optree from migen.flow.actor import Sink, Source from migen.actorlib.fifo import SyncFIFO -from liteusb.ftdi.std import * +from misoclib.com.liteusb.common import * class CRCEngine(Module): """Cyclic Redundancy Check Engine diff --git a/misoclib/com/liteusb/core/depacketizer.py b/misoclib/com/liteusb/core/depacketizer.py index d1b75a915..97400df3e 100644 --- a/misoclib/com/liteusb/core/depacketizer.py +++ b/misoclib/com/liteusb/core/depacketizer.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.actorlib.structuring import * from migen.genlib.fsm import FSM, NextState -from liteusb.ftdi.std import * +from misoclib.com.liteusb.common import * class FtdiDepacketizer(Module): def __init__(self, timeout=10): diff --git a/misoclib/com/liteusb/core/packetizer.py b/misoclib/com/liteusb/core/packetizer.py index bba3ab88c..de9c69ed4 100644 --- a/misoclib/com/liteusb/core/packetizer.py +++ b/misoclib/com/liteusb/core/packetizer.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.actorlib.structuring import * from migen.genlib.fsm import FSM, NextState -from liteusb.ftdi.std import * +from misoclib.com.liteusb.common import * class FtdiPacketizer(Module): def __init__(self): diff --git a/misoclib/com/liteusb/frontend/crossbar.py b/misoclib/com/liteusb/frontend/crossbar.py index d1771c049..cc548a43a 100644 --- a/misoclib/com/liteusb/frontend/crossbar.py +++ b/misoclib/com/liteusb/frontend/crossbar.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.genlib.roundrobin import * from migen.genlib.record import Record -from liteusb.ftdi.std import * +from misoclib.com.liteusb.common import * class FtdiCrossbar(Module): def __init__(self, masters, slave=None): diff --git a/misoclib/com/liteusb/frontend/dma.py b/misoclib/com/liteusb/frontend/dma.py index 6aff0f0c9..bcbbe4fbc 100644 --- a/misoclib/com/liteusb/frontend/dma.py +++ b/misoclib/com/liteusb/frontend/dma.py @@ -8,7 +8,7 @@ from migen.genlib.record import Record from misoclib.mem.sdram.frontend import dma_lasmi -from liteusb.ftdi.std import * +from misoclib.com.liteusb.common import * class FtdiDMAWriter(Module, AutoCSR): def __init__(self, lasmim): diff --git a/misoclib/com/liteusb/frontend/uart.py b/misoclib/com/liteusb/frontend/uart.py index 64833f4ce..2712d7b93 100644 --- a/misoclib/com/liteusb/frontend/uart.py +++ b/misoclib/com/liteusb/frontend/uart.py @@ -3,7 +3,7 @@ from migen.bank.description import * from migen.bank.eventmanager import * from migen.genlib.fifo import SyncFIFOBuffered -from liteusb.ftdi.std import * +from misoclib.com.liteusb.common import * class FtdiUART(Module, AutoCSR): def __init__(self, tag, fifo_depth=64):