diff --git a/litex_setup.py b/litex_setup.py
index 71ad35a76..c660d7e0c 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -68,7 +68,6 @@ class GitRepo:
 git_repos = {
     # HDL.
     "migen":    GitRepo(url="https://github.com/m-labs/", clone="recursive"),
-    "amaranth": GitRepo(url="https://github.com/amaranth-lang/", branch="main"),
 
     # LiteX SoC builder
     "pythondata-software-picolibc":    GitRepo(url="https://github.com/litex-hub/", clone="recursive"),
@@ -116,7 +115,6 @@ minimal_repos = ["migen", "litex"]
 
 # Standard: Migen + LiteX + Cores + Software + Popular CPUs (LM32, Mor1kx, SERV, VexRiscv).
 standard_repos = list(git_repos.keys())
-standard_repos.remove("amaranth")
 standard_repos.remove("pythondata-cpu-picorv32")
 standard_repos.remove("pythondata-cpu-rocket")
 standard_repos.remove("pythondata-cpu-minerva")
diff --git a/test/test_cpu.py b/test/test_cpu.py
index 6200fbde2..02047107b 100644
--- a/test/test_cpu.py
+++ b/test/test_cpu.py
@@ -56,10 +56,6 @@ class TestCPU(unittest.TestCase):
     def test_picorv32(self):
         self.assertTrue(self.boot_test("picorv32"))
 
-    # FIXME: Wait for Aramanth/Minerva to stabilize.
-    #def test_minerva(self):
-    #    self.assertTrue(self.boot_test("minerva"))
-
     # OpenRISC CPUs.
     #def test_mor1kx(self):
     #    self.assertTrue(self.boot_test("mor1kx"))