From eedebd8adb6f7318f7d38b8a24d15446c1a2e6bc Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 30 Oct 2023 17:17:16 +0100 Subject: [PATCH] litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width --- litex/soc/cores/cpu/__init__.py | 6 ++++-- litex/soc/integration/soc.py | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py index 0ebc65923..1d816b3dd 100644 --- a/litex/soc/cores/cpu/__init__.py +++ b/litex/soc/cores/cpu/__init__.py @@ -50,11 +50,9 @@ class CPU(LiteXModule): class CPUNone(CPU): variants = ["standard"] - data_width = 32 endianness = "little" reset_address = 0x00000000 reset_address_check = False - io_regions = {0x0000_0000: 0x1_0000_0000} # origin, length periph_buses = [] memory_buses = [] mem_map = { @@ -63,6 +61,10 @@ class CPUNone(CPU): "spiflash" : 0x1000_0000, # FIXME: Remove. } + def __init__(self, data_width=32, addr_width=32): + self.io_regions = {0: int(2**float(addr_width))} # origin, length + self.data_width = data_width + # CPUs GCC Triples --------------------------------------------------------------------------------- CPU_GCC_TRIPLE_RISCV64 = ( diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 7e5588658..ad462d429 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1082,7 +1082,10 @@ class SoC(LiteXModule, SoCCoreCompat): colorer("\n - ".join(sorted(cpu_cls.variants))))) raise SoCError() self.check_if_exists("cpu") - self.cpu = cpu_cls(self.platform, variant) + if cpu_cls is cpu.CPUNone: + self.cpu = cpu_cls(self.bus.data_width, self.bus.address_width) + else: + self.cpu = cpu_cls(self.platform, variant) self.logger.info("CPU {} {}.".format( colorer(name, color="underline"), colorer("added", color="green")))