diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 0388cdda0..8ccb4ff0e 100644
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -26,6 +26,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
 sim: mkdir $(OBJS_SIM)
 	verilator -Wno-fatal -O3 --cc dut.v --exe \
 		$(SRCS_SIM_CPP) $(OBJS_SIM) \
+		--top-module dut \
 		-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
 		-LDFLAGS "$(LDFLAGS)" \
 		-trace $(INC_DIR)
diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 312d51e3f..d4092b658 100644
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -146,7 +146,7 @@ class SimVerilatorToolchain:
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
 
-        v_output = platform.get_verilog(fragment)
+        v_output = platform.get_verilog(fragment, name=build_name)
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_output.write("dut.v")