From ef6c517daddf5700b9e35db5664134e39733e615 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Tue, 23 Jan 2018 01:15:28 +0000 Subject: [PATCH] Build top module as 'dut' in Verilator and set it as top-level. When building a design with PicoRV32 we end up with multiple top-level modules and Verilator becomes confused as to which is the right one. This change ensures the dut.v generated by the sim build process has it's top-level name set to 'dut' and that verilator is invoked with this name. --- litex/build/sim/core/Makefile | 1 + litex/build/sim/verilator.py | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile index 0388cdda0..8ccb4ff0e 100644 --- a/litex/build/sim/core/Makefile +++ b/litex/build/sim/core/Makefile @@ -26,6 +26,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c sim: mkdir $(OBJS_SIM) verilator -Wno-fatal -O3 --cc dut.v --exe \ $(SRCS_SIM_CPP) $(OBJS_SIM) \ + --top-module dut \ -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \ -LDFLAGS "$(LDFLAGS)" \ -trace $(INC_DIR) diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index 312d51e3f..d4092b658 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -146,7 +146,7 @@ class SimVerilatorToolchain: fragment = fragment.get_fragment() platform.finalize(fragment) - v_output = platform.get_verilog(fragment) + v_output = platform.get_verilog(fragment, name=build_name) named_sc, named_pc = platform.resolve_signals(v_output.ns) v_output.write("dut.v")