From ef904a14e18bcd41b8e7dc47e4c277fa50dd8138 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Wed, 10 May 2023 05:22:23 +0700 Subject: [PATCH] AvalonMM2Wishbone: fix burst reads (#1686) --- litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py b/litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py index 5a75157c0..2177dbfdf 100644 --- a/litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py +++ b/litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py @@ -59,7 +59,6 @@ class AvalonMM2Wishbone(Module): self.comb += [ avl.waitrequest.eq(~(wb.ack | wb.err) | burst_read), avl.readdata.eq(readdata), - avl.readdatavalid.eq(readdatavalid), ] # Avalon -> Wishbone @@ -79,6 +78,7 @@ class AvalonMM2Wishbone(Module): self.submodules.fsm = fsm = FSM(reset_state="SINGLE") fsm.act("SINGLE", burst_cycle.eq(0), + avl.readdatavalid.eq(readdatavalid), wb.sel.eq(avl.byteenable), wb.cti.eq(wishbone.CTI_BURST_NONE), If(avl.burstcount > 1, @@ -97,6 +97,7 @@ class AvalonMM2Wishbone(Module): ) ) fsm.act("BURST-WRITE", + avl.readdatavalid.eq(0), burst_cycle.eq(1), wb.sel.eq(avl.byteenable), wb.cti.eq(wishbone.CTI_BURST_INCREMENTING), @@ -113,6 +114,7 @@ class AvalonMM2Wishbone(Module): ) ) fsm.act("BURST-READ", + avl.readdatavalid.eq(0), burst_cycle.eq(1), burst_read.eq(1), wb.stb.eq(1), @@ -122,6 +124,7 @@ class AvalonMM2Wishbone(Module): wb.cti.eq(wishbone.CTI_BURST_END) ), If(wb.ack, + avl.readdatavalid.eq(1), NextValue(burst_address, burst_address + word_width), NextValue(burst_count, burst_count - 1) ),