diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index c10d6fb2d..69cfc2a41 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -63,8 +63,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq,
-                cmd_latency  = 1)
+                sys_clk_freq = sys_clk_freq)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 15f312eb8..320d0ca78 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -65,8 +65,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq,
-                cmd_latency  = 1)
+                sys_clk_freq = sys_clk_freq)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 7a9111d9c..83a4e684f 100755
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -74,8 +74,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 200e6,
-                cmd_latency      = 1)
+                iodelay_clk_freq = 200e6)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 3d5fbd124..8585b1ed0 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -114,27 +114,23 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
     elif memtype in ["DDR2", "DDR3"]:
         # Settings from s7ddrphy
         tck             = 2/(2*nphases*clk_freq)
-        cmd_latency     = 0
         cl, cwl         = get_cl_cw(memtype, tck)
         cl_sys_latency  = get_sys_latency(nphases, cl)
-        cwl             = cwl + cmd_latency
         cwl_sys_latency = get_sys_latency(nphases, cwl)
         rdphase         = get_sys_phase(nphases, cl_sys_latency, cl)
         wrphase         = get_sys_phase(nphases, cwl_sys_latency, cwl)
-        read_latency    = 2 + cl_sys_latency + 2 + 3
-        write_latency   = cwl_sys_latency
+        read_latency    = cl_sys_latency + 6
+        write_latency   = cwl_sys_latency - 1
     elif memtype == "DDR4":
         # Settings from usddrphy
         tck             = 2/(2*nphases*clk_freq)
-        cmd_latency     = 0
         cl, cwl         = get_cl_cw(memtype, tck)
         cl_sys_latency  = get_sys_latency(nphases, cl)
-        cwl             = cwl + cmd_latency
         cwl_sys_latency = get_sys_latency(nphases, cwl)
         rdphase         = get_sys_phase(nphases, cl_sys_latency, cl)
         wrphase         = get_sys_phase(nphases, cwl_sys_latency, cwl)
-        read_latency    = 2 + cl_sys_latency + 1 + 3
-        write_latency   = cwl_sys_latency
+        read_latency    = cl_sys_latency + 5
+        write_latency   = cwl_sys_latency - 1
 
     sdram_phy_settings = {
         "nphases":       nphases,