From f1606dbc7252804af445af12e5130a387950553f Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Jan 2020 17:39:23 +0100
Subject: [PATCH] tools/litex_sim: use default integrated_rom_size

---
 litex/tools/litex_sim.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 99a0e1694..ecf3edf63 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -107,7 +107,6 @@ class SimSoC(SoCSDRAM):
 
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size = 0x8000,
             ident               = "LiteX Simulation", ident_version=True,
             with_uart           = False,
             **kwargs)