From f224036138b1dbecba294b75378c949f4b5538a1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 5 Apr 2022 19:53:00 +0200 Subject: [PATCH] stream/ClockDomainCrossing: Revert with_common_rst to False by default (Previous behavior). This seems to cause issues in simulation on some cores, this will first have to be fixed before using it as default. Cores requiring it will set it to True explicitly for now. --- litex/soc/interconnect/stream.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index 530497ccc..1543cdfaa 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -242,7 +242,7 @@ class AsyncFIFO(_FIFOWrapper): # ClockDomainCrossing ------------------------------------------------------------------------------ class ClockDomainCrossing(Module): - def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=True): + def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=False): self.sink = Endpoint(layout) self.source = Endpoint(layout)