From 2562ae5f632d4589c2c597c2470ce82a0c081b14 Mon Sep 17 00:00:00 2001 From: Andy Kitchen Date: Thu, 25 Nov 2021 22:36:52 +1100 Subject: [PATCH] fix FemtoRV reset signal --- litex/soc/cores/cpu/femtorv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/femtorv/core.py b/litex/soc/cores/cpu/femtorv/core.py index 305b1f80f..9ff231665 100644 --- a/litex/soc/cores/cpu/femtorv/core.py +++ b/litex/soc/cores/cpu/femtorv/core.py @@ -95,7 +95,7 @@ class FemtoRV(CPU): # Clk / Rst. i_clk = ClockSignal("sys"), - i_reset = ~ResetSignal("sys"), # Active Low. + i_reset = ~(ResetSignal("sys") | self.reset), # Active Low. # I/D Bus. o_mem_addr = mbus.addr,