From f26769eb4da141226b44cc68e58dd707cb029907 Mon Sep 17 00:00:00 2001 From: Piotr Binkowski Date: Wed, 16 Dec 2020 17:30:04 +0100 Subject: [PATCH] interconnect/axi: add connect_to_pads to full AXI --- litex/soc/interconnect/axi.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 29ab122c8..99b377db1 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -140,7 +140,16 @@ class AXIInterface: self.r = stream.Endpoint(r_description(data_width, id_width)) def connect_to_pads(self, pads, mode="master"): - return connect_to_pads(self, pads, mode) + r = connect_to_pads(self, pads, mode) + + if mode == "master": + r.append(pads.wlast.eq(self.w.last)) + r.append(self.r.last.eq(pads.rlast)) + else: + r.append(pads.rlast.eq(self.r.last)) + r.append(self.w.last.eq(pads.wlast)) + + return r def get_ios(self, bus_name="wb"): subsignals = []