From 46788f2d9c1d8899ebcf648744cc89a2e1d358dd Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Mon, 4 Jul 2022 12:47:09 +0200 Subject: [PATCH 01/11] integration/soc Add accessible_region to add_memory_buses Enables CPUs to know which memory addresses are accessible via the connected memory_bus. --- litex/soc/cores/cpu/naxriscv/core.py | 6 +++++- litex/soc/cores/cpu/vexriscv_smp/core.py | 2 +- litex/soc/integration/soc.py | 9 ++++++--- 3 files changed, 12 insertions(+), 5 deletions(-) mode change 100644 => 100755 litex/soc/cores/cpu/naxriscv/core.py mode change 100644 => 100755 litex/soc/integration/soc.py diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py old mode 100644 new mode 100755 index 63e63ec07..2d936ddf0 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -396,7 +396,7 @@ class NaxRiscv(CPU): ) soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False)) - def add_memory_buses(self, address_width, data_width): + def add_memory_buses(self, address_width, data_width, accessible_region): nax_data_width = 64 nax_burst_size = 64 assert data_width >= nax_data_width # FIXME: Only supporting up-conversion for now. @@ -460,6 +460,10 @@ class NaxRiscv(CPU): i_ram_dbus_rresp = dbus.r.resp, i_ram_dbus_rlast = dbus.r.last, ) + self.scala_args.append('mem-region-origin=0x{accessible_region.origin:x}' + .format(accessible_region=accessible_region)) + self.scala_args.append('mem-region-length=0x{accessible_region.size:x}' + .format(accessible_region=accessible_region)) def do_finalize(self): assert hasattr(self, "reset_address") diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index e6728711c..40f7d8d35 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -430,7 +430,7 @@ class VexRiscvSMP(CPU): ) soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False)) - def add_memory_buses(self, address_width, data_width): + def add_memory_buses(self, address_width, data_width, accessible_region): VexRiscvSMP.litedram_width = data_width from litedram.common import LiteDRAMNativePort diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py old mode 100644 new mode 100755 index d20e33680..6f6149693 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1460,13 +1460,16 @@ class LiteXSoC(SoC): sdram_size = min(sdram_size, size) # Add SDRAM region. - self.bus.add_region("main_ram", SoCRegion(origin=self.mem_map.get("main_ram", origin), size=sdram_size)) + main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin), + size=sdram_size) + self.bus.add_region("main_ram", main_ram_region) # Add CPU's direct memory buses (if not already declared) ---------------------------------- if hasattr(self.cpu, "add_memory_buses"): self.cpu.add_memory_buses( - address_width = 32, - data_width = sdram.crossbar.controller.data_width + address_width = 32, + data_width = sdram.crossbar.controller.data_width, + accessible_region = main_ram_region ) # Connect CPU's direct memory buses to LiteDRAM -------------------------------------------- From 37360587e39886ec6ff1e93dd2aab46201fcb393 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Tue, 30 Aug 2022 15:47:59 +0200 Subject: [PATCH 02/11] Change SocRegion readonly definition From (mode == "r") to ("w" not in mode). This allows to have more possible modes than r & w. --- litex/soc/integration/soc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 6f6149693..0f8df306c 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -883,7 +883,7 @@ class SoC(Module): "axi" : axi.AXILiteInterface, # FIXME: Use AXI-Lite for now, create AXISRAM. }[self.bus.standard] ram_bus = interface_cls(data_width=self.bus.data_width, bursting=self.bus.bursting) - ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"), name=name) + ram = ram_cls(size, bus=ram_bus, init=contents, read_only=("w" not in mode), name=name) self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode)) self.check_if_exists(name) self.logger.info("RAM {} {} {}.".format( @@ -902,7 +902,7 @@ class SoC(Module): colorer(name), colorer(f"0x{4*len(contents):x}"))) getattr(self, name).mem.init = contents - if auto_size and self.bus.regions[name].mode == "r": + if auto_size and "w" not in self.bus.regions[name].mode: self.logger.info("Auto-Resizing ROM {} from {} to {}.".format( colorer(name), colorer(f"0x{self.bus.regions[name].size:x}"), From 76c0754d1e8e827bb6028964ada987f62a3be881 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Tue, 30 Aug 2022 15:57:25 +0200 Subject: [PATCH 03/11] Add new SocRegion mode "x" (executable) Defaults: SoCRegion/SoCIORegion/SoCCSRRegion: RW ROMs: RX RAMs: RWX --- litex/soc/integration/soc.py | 4 ++-- litex/soc/integration/soc_core.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 0f8df306c..1c912e211 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -871,7 +871,7 @@ class SoC(Module): colorer("added", color="green"))) setattr(self.submodules, name, SoCController(**kwargs)) - def add_ram(self, name, origin, size, contents=[], mode="rw"): + def add_ram(self, name, origin, size, contents=[], mode="rwx"): ram_cls = { "wishbone": wishbone.SRAM, "axi-lite": axi.AXILiteSRAM, @@ -894,7 +894,7 @@ class SoC(Module): if contents != []: self.add_config(f"{name}_INIT", 1) - def add_rom(self, name, origin, size, contents=[], mode="r"): + def add_rom(self, name, origin, size, contents=[], mode="rx"): self.add_ram(name, origin, size, contents, mode=mode) def init_rom(self, name, contents=[], auto_size=True): diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index d7208903f..7329fc775 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -78,7 +78,7 @@ class SoCCore(LiteXSoC): # ROM parameters integrated_rom_size = 0, - integrated_rom_mode = "r", + integrated_rom_mode = "rx", integrated_rom_init = [], # SRAM parameters From 3e42133abd472a5441727d741ea67508e5681a36 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Tue, 30 Aug 2022 16:22:29 +0200 Subject: [PATCH 04/11] Change SDRAM region to RWX --- litex/soc/integration/soc.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 1c912e211..4e9a4b87c 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1461,7 +1461,8 @@ class LiteXSoC(SoC): # Add SDRAM region. main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin), - size=sdram_size) + size=sdram_size, + mode="rwx") self.bus.add_region("main_ram", main_ram_region) # Add CPU's direct memory buses (if not already declared) ---------------------------------- From 027306972a0104517471e68df9bcce77079f416d Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Tue, 30 Aug 2022 16:41:39 +0200 Subject: [PATCH 05/11] Naxriscv now scans for executable mem regions and forwards that info to the scala build process Format: --scala-args=executable-region=(origin, length), --scala-args=exe... --- litex/soc/cores/cpu/naxriscv/core.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 2d936ddf0..435029dac 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -395,6 +395,7 @@ class NaxRiscv(CPU): o_peripheral_clint_rresp = clintbus.r.resp, ) soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False)) + self.soc = soc # Save SoC instance to retrieve the final mem layout on finalization def add_memory_buses(self, address_width, data_width, accessible_region): nax_data_width = 64 @@ -467,8 +468,14 @@ class NaxRiscv(CPU): def do_finalize(self): assert hasattr(self, "reset_address") - self.find_scala_files() + + # Find mem regions with executable flag + for region in self.soc.bus.regions.values(): + if 'x' in region.mode: + self.scala_args.append('executable-region=(0x{region.origin:x},0x{region.size:x})' + .format(region=region)) + self.generate_netlist_name(self.reset_address) # Do verilog instance. From fb2a52a6c7b2a447b95a9bf0e05d7cac16532784 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Wed, 31 Aug 2022 13:25:27 +0200 Subject: [PATCH 06/11] Generate naxriscv mem region parameters in new format --- litex/soc/cores/cpu/naxriscv/core.py | 28 ++++++++++++++++++---------- litex/soc/integration/soc.py | 5 ++--- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 435029dac..ee445d41d 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -196,6 +196,7 @@ class NaxRiscv(CPU): md5_hash.update(str(NaxRiscv.xlen).encode('utf-8')) md5_hash.update(str(NaxRiscv.jtag_tap).encode('utf-8')) md5_hash.update(str(NaxRiscv.jtag_instruction).encode('utf-8')) + md5_hash.update(str(NaxRiscv.memory_regions).encode('utf-8')) for args in NaxRiscv.scala_args: md5_hash.update(args.encode('utf-8')) for file in NaxRiscv.scala_paths: @@ -235,6 +236,8 @@ class NaxRiscv(CPU): gen_args.append(f"--netlist-directory={vdir}") gen_args.append(f"--reset-vector={reset_address}") gen_args.append(f"--xlen={NaxRiscv.xlen}") + for region in NaxRiscv.memory_regions: + gen_args.append(f"--memory-region={region[0]},{region[1]},{region[2]}") for args in NaxRiscv.scala_args: gen_args.append(f"--scala-args={args}") if(NaxRiscv.jtag_tap) : @@ -397,7 +400,7 @@ class NaxRiscv(CPU): soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False)) self.soc = soc # Save SoC instance to retrieve the final mem layout on finalization - def add_memory_buses(self, address_width, data_width, accessible_region): + def add_memory_buses(self, address_width, data_width): nax_data_width = 64 nax_burst_size = 64 assert data_width >= nax_data_width # FIXME: Only supporting up-conversion for now. @@ -461,20 +464,25 @@ class NaxRiscv(CPU): i_ram_dbus_rresp = dbus.r.resp, i_ram_dbus_rlast = dbus.r.last, ) - self.scala_args.append('mem-region-origin=0x{accessible_region.origin:x}' - .format(accessible_region=accessible_region)) - self.scala_args.append('mem-region-length=0x{accessible_region.size:x}' - .format(accessible_region=accessible_region)) def do_finalize(self): assert hasattr(self, "reset_address") self.find_scala_files() - # Find mem regions with executable flag - for region in self.soc.bus.regions.values(): - if 'x' in region.mode: - self.scala_args.append('executable-region=(0x{region.origin:x},0x{region.size:x})' - .format(region=region)) + # Generate memory map from CPU perspective + # naxriscv modes: + # r,w : regular memory load/store + # i,o : peripheral memory load/store + # x : instruction fetchable (execute) + # litex modes: + # rwx : load, store, execute (everything is peripheral per default) + NaxRiscv.memory_regions = [] + for name, region in self.soc.bus.regions.items(): + if len(self.memory_buses) and name == 'main_ram': + mode = region.mode + else: + mode = region.mode.replace('r', 'i').replace('w', 'o') + NaxRiscv.memory_regions.append( (region.origin, region.size, mode) ) self.generate_netlist_name(self.reset_address) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 4e9a4b87c..6eccd5c71 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1468,9 +1468,8 @@ class LiteXSoC(SoC): # Add CPU's direct memory buses (if not already declared) ---------------------------------- if hasattr(self.cpu, "add_memory_buses"): self.cpu.add_memory_buses( - address_width = 32, - data_width = sdram.crossbar.controller.data_width, - accessible_region = main_ram_region + address_width = 32, + data_width = sdram.crossbar.controller.data_width ) # Connect CPU's direct memory buses to LiteDRAM -------------------------------------------- From b63e445ade6017cb1ee33d78bdefa8aec7aa9d88 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Wed, 31 Aug 2022 15:31:37 +0200 Subject: [PATCH 07/11] cpu/NaxRiscv: Update to new version --- litex/soc/cores/cpu/naxriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 25884821b..b43d98ef5 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -228,7 +228,7 @@ class NaxRiscv(CPU): ndir = os.path.join(vdir, "ext", "NaxRiscv") sdir = os.path.join(vdir, "ext", "SpinalHDL") - NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "b13c0aad") + NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "7c61b64") NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "a130f7b7") gen_args = [] From c8bd747e0fa04743e963e0d5b5c6225bd34a592a Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Fri, 2 Sep 2022 12:13:21 +0200 Subject: [PATCH 08/11] Remove linker regions from naxriscv mem list Assume linker=True SoCRegions are virtual only. --- litex/soc/cores/cpu/naxriscv/core.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index b43d98ef5..80c5f4dd8 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -478,6 +478,8 @@ class NaxRiscv(CPU): # rwx : load, store, execute (everything is peripheral per default) NaxRiscv.memory_regions = [] for name, region in self.soc.bus.regions.items(): + if region.linker: # remove virtual regions + continue if len(self.memory_buses) and name == 'main_ram': mode = region.mode else: From a04f20880f908c60f68d49d1048b334a97c3f8a4 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Thu, 8 Sep 2022 17:33:20 +0200 Subject: [PATCH 09/11] Change naxriscv memory-region format It now has a mode and a bus field. modes: rwxc (read, write, execute, cachable) bus: pm (peripheral, memory) --- litex/soc/cores/cpu/naxriscv/core.py | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 80c5f4dd8..d4c211817 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -237,7 +237,7 @@ class NaxRiscv(CPU): gen_args.append(f"--reset-vector={reset_address}") gen_args.append(f"--xlen={NaxRiscv.xlen}") for region in NaxRiscv.memory_regions: - gen_args.append(f"--memory-region={region[0]},{region[1]},{region[2]}") + gen_args.append(f"--memory-region={region[0]},{region[1]},{region[2]},{region[3]}") for args in NaxRiscv.scala_args: gen_args.append(f"--scala-args={args}") if(NaxRiscv.jtag_tap) : @@ -477,14 +477,18 @@ class NaxRiscv(CPU): # litex modes: # rwx : load, store, execute (everything is peripheral per default) NaxRiscv.memory_regions = [] + for name, region in self.soc.bus.io_regions.items(): + NaxRiscv.memory_regions.append( (region.origin, region.size, "io", "p") ) # IO is only allowed on the p bus for name, region in self.soc.bus.regions.items(): if region.linker: # remove virtual regions continue - if len(self.memory_buses) and name == 'main_ram': - mode = region.mode + if len(self.memory_buses) and name == 'main_ram': # m bus + bus = "m" else: - mode = region.mode.replace('r', 'i').replace('w', 'o') - NaxRiscv.memory_regions.append( (region.origin, region.size, mode) ) + bus = "p" + mode = region.mode + mode += "c" if region.cached else "" + NaxRiscv.memory_regions.append( (region.origin, region.size, mode, bus) ) self.generate_netlist_name(self.reset_address) From 14160ce7e3ff03205c64b723877f9e175b13c1f5 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 9 Sep 2022 11:23:24 +0200 Subject: [PATCH 10/11] cpu/NaxRiscv update nax with peripheral memory region --- litex/soc/cores/cpu/naxriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index d4c211817..234e5784e 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -228,7 +228,7 @@ class NaxRiscv(CPU): ndir = os.path.join(vdir, "ext", "NaxRiscv") sdir = os.path.join(vdir, "ext", "SpinalHDL") - NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "7c61b64") + NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "cb2a598a") NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "a130f7b7") gen_args = [] From 6367fc6cabc58e35a9bee3f21163772f43baf1a7 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Fri, 9 Sep 2022 13:19:36 +0200 Subject: [PATCH 11/11] update naxriscv comments --- litex/soc/cores/cpu/naxriscv/core.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 234e5784e..ece699037 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -471,11 +471,11 @@ class NaxRiscv(CPU): # Generate memory map from CPU perspective # naxriscv modes: - # r,w : regular memory load/store - # i,o : peripheral memory load/store - # x : instruction fetchable (execute) - # litex modes: - # rwx : load, store, execute (everything is peripheral per default) + # r,w,x,c : readable, writeable, executable, caching allowed + # io : IO region (Implies P bus, preserve memory order, no dcache) + # naxriscv bus: + # p : peripheral + # m : memory NaxRiscv.memory_regions = [] for name, region in self.soc.bus.io_regions.items(): NaxRiscv.memory_regions.append( (region.origin, region.size, "io", "p") ) # IO is only allowed on the p bus