From f3829cf0819c2e5d0ebc6cffb9569f9f46191549 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 20 Feb 2020 16:16:07 +0100 Subject: [PATCH] integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs. --- litex/soc/integration/soc.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index bd896e0bd..127aecec8 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1001,4 +1001,5 @@ class LiteXSoC(SoC): self.add_config("L2_SIZE", l2_cache_size) # Wishbone Slave <--> LiteDRAM bridge -------------------------------------------------- - self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port) + self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port, + base_address = self.bus.regions["main_ram"].origin)