diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index fd736f611..31bef380c 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1342,6 +1342,7 @@ class LiteXSoC(SoC):
         # Imports
         from liteeth.core import LiteEthUDPIPCore
         from liteeth.frontend.etherbone import LiteEthEtherbone
+        from liteeth.phy.model import LiteEthPHYModel
         # Core
         ethcore = LiteEthUDPIPCore(
             phy         = phy,
@@ -1368,12 +1369,13 @@ class LiteXSoC(SoC):
         else:
             eth_rx_clk = phy.cd_eth_rx.clk
             eth_tx_clk = phy.cd_eth_tx.clk
-        self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
-        self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            eth_rx_clk,
-            eth_tx_clk)
+        if not isinstance(phy, LiteEthPHYModel):
+            self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
+            self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
+            self.platform.add_false_path_constraints(
+                self.crg.cd_sys.clk,
+                eth_rx_clk,
+                eth_tx_clk)
 
     # Add SPI Flash --------------------------------------------------------------------------------
     def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None):