From f3b287adddcabb2ffdf6523898b56dc257b1aaa7 Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Sun, 25 Feb 2024 11:25:49 +1100
Subject: [PATCH] cores/spi_mmap: add 24-bit slot length

---
 litex/soc/cores/spi/spi_mmap.py |  6 +++++-
 test/test_spi_mmap.py           | 13 +++++++++++++
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/litex/soc/cores/spi/spi_mmap.py b/litex/soc/cores/spi/spi_mmap.py
index 58ea9e1fd..452c6a6b2 100644
--- a/litex/soc/cores/spi/spi_mmap.py
+++ b/litex/soc/cores/spi/spi_mmap.py
@@ -35,6 +35,7 @@ SPI_SLOT_MODE_3             = 0b11
 SPI_SLOT_LENGTH_32B         = 0b00
 SPI_SLOT_LENGTH_16B         = 0b01
 SPI_SLOT_LENGTH_8B          = 0b10
+SPI_SLOT_LENGTH_24B         = 0b11
 
 SPI_SLOT_BITORDER_MSB_FIRST = 0b0
 SPI_SLOT_BITORDER_LSB_FIRST = 0b1
@@ -337,7 +338,7 @@ class SPICtrl(LiteXModule):
                     ("``0b00``", "32-bit Max."),
                     ("``0b01``", "16-bit Max."),
                     ("``0b10``", " 8-bit Max."),
-                    ("``0b11``", "Reserved."),
+                    ("``0b11``", "24-bit Max."),
                 ], reset=default_slot_length),
                 CSRField("bitorder", size=1, offset=5, values=[
                     ("``0b0``", "MSB-First."),
@@ -543,6 +544,7 @@ class SPIEngine(LiteXModule):
         })
         self.comb += Case(ctrl.get_ctrl("length",  cs=sink.cs), {
             SPI_SLOT_LENGTH_32B : spi_length_max.eq(32), # 32-bit access max.
+            SPI_SLOT_LENGTH_24B : spi_length_max.eq(24), # 24-bit access max.
             SPI_SLOT_LENGTH_16B : spi_length_max.eq(16), # 16-bit access max.
             SPI_SLOT_LENGTH_8B  : spi_length_max.eq( 8), #  8-bit access max.
         })
@@ -594,6 +596,7 @@ class SPIEngine(LiteXModule):
                 Case(spi.length, {
                      8 : spi.mosi[24:32].eq(sink.data[0: 8]),
                     16 : spi.mosi[16:32].eq(sink.data[0:16]),
+                    24 : spi.mosi[ 8:32].eq(sink.data[0:24]),
                     32 : spi.mosi[ 0:32].eq(sink.data[0:32]),
                 }),
                 # RX copy.
@@ -607,6 +610,7 @@ class SPIEngine(LiteXModule):
                 Case(spi.length, {
                      8 : source.data[0: 8].eq(spi.miso[::-1][24:32]),
                     16 : source.data[0:16].eq(spi.miso[::-1][16:32]),
+                    24 : source.data[0:24].eq(spi.miso[::-1][ 8:32]),
                     32 : source.data[0:32].eq(spi.miso[::-1][ 0:32]),
                 })
             )
diff --git a/test/test_spi_mmap.py b/test/test_spi_mmap.py
index 4c26baa31..c5465bcc6 100644
--- a/test/test_spi_mmap.py
+++ b/test/test_spi_mmap.py
@@ -18,6 +18,7 @@ from litex.soc.cores.spi.spi_mmap import (
     SPI_SLOT_BITORDER_LSB_FIRST,
     SPI_SLOT_BITORDER_MSB_FIRST,
     SPI_SLOT_LENGTH_16B,
+    SPI_SLOT_LENGTH_24B,
     SPI_SLOT_LENGTH_32B,
     SPI_SLOT_LENGTH_8B,
     SPI_SLOT_MODE_0,
@@ -165,6 +166,10 @@ class TestSPIMMAP(unittest.TestCase):
                 spi_length = 32
                 sel = 0b1111
                 width = 8
+            if length == SPI_SLOT_LENGTH_24B:
+                spi_length = 24
+                sel = 0b1111
+                width = 6
             if length == SPI_SLOT_LENGTH_16B:
                 spi_length = 16
                 sel = 0b0011
@@ -232,6 +237,14 @@ class TestSPIMMAP(unittest.TestCase):
         data = [0x12345678, 0x9ABCDEF0]
         self.mmap_test(SPI_SLOT_LENGTH_32B, SPI_SLOT_BITORDER_MSB_FIRST, data, "mmap_32_msb.vcd")
 
+    def test_spi_mmap_24_lsb(self):
+        data = [0x123456, 0x789ABC, 0xDEF012]
+        self.mmap_test(SPI_SLOT_LENGTH_24B, SPI_SLOT_BITORDER_LSB_FIRST, data, "mmap_24_lsb.vcd")
+
+    def test_spi_mmap_24_msb(self):
+        data = [0x123456, 0x789ABC, 0xDEF012]
+        self.mmap_test(SPI_SLOT_LENGTH_24B, SPI_SLOT_BITORDER_MSB_FIRST, data, "mmap_24_msb.vcd")
+
     # 16 bit write to 16bit slot
     def test_spi_mmap_16_lsb(self):
         data = [0x1234, 0x5678, 0x9ABC, 0xDEF0]