From f408527dd46a04b6224e5b2e36d5b98d644d703b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Jan 2020 08:49:23 +0100 Subject: [PATCH] soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus. Toolchain can be downloaded from https://toolchains.bootlin.com/ --- litex/soc/cores/cpu/minerva/core.py | 3 ++- litex/soc/cores/cpu/picorv32/core.py | 3 ++- litex/soc/cores/cpu/rocket/core.py | 2 +- litex/soc/cores/cpu/vexriscv/core.py | 3 ++- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index b592e34ca..9bc970895 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -17,7 +17,8 @@ class Minerva(CPU): name = "minerva" data_width = 32 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") + gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", + "riscv64-linux") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index cc03cdb89..c2122677c 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -34,7 +34,8 @@ class PicoRV32(CPU): name = "picorv32" data_width = 32 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") + gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", + "riscv64-linux") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 899043bda..108a49678 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -67,7 +67,7 @@ class RocketRV64(CPU): name = "rocket" data_width = 64 endianness = "little" - gcc_triple = ("riscv64-unknown-elf") + gcc_triple = ("riscv64-unknown-elf", "riscv64-linux") linker_output_format = "elf64-littleriscv" io_regions = {0x10000000: 0x70000000} # origin, length diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index c281943e2..100ce4be7 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -78,7 +78,8 @@ class VexRiscv(CPU, AutoCSR): name = "vexriscv" data_width = 32 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") + gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", + "riscv64-linux") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length