From f41ae88d1c302185fe360714a6a8debd0d24aff4 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 14 Nov 2023 11:34:13 +0100 Subject: [PATCH] soc/cores/clock/efinix: create_clkin: adding lvds_input optional parameter (required when used with LVDS serdes) --- litex/soc/cores/clock/efinix.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/clock/efinix.py b/litex/soc/cores/clock/efinix.py index 14fe6414c..fae23d7d4 100644 --- a/litex/soc/cores/clock/efinix.py +++ b/litex/soc/cores/clock/efinix.py @@ -55,7 +55,7 @@ class EFINIXPLL(LiteXModule): self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset) self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked")) - def register_clkin(self, clkin, freq, name=""): + def register_clkin(self, clkin, freq, name="", lvds_input=False): block = self.platform.toolchain.ifacewriter.get_block(self.name) block["input_clock_name"] = self.platform.get_pin_name(clkin) @@ -79,7 +79,7 @@ class EFINIXPLL(LiteXModule): self.logger.error("Cannot find a pll with {} as input".format(pad_name)) quit() - block["input_clock"] = "EXTERNAL" + block["input_clock"] = "EXTERNAL" if not lvds_input else "LVDS_RX" block["input_clock_pad"] = pin_name block["resource"] = pll_res block["clock_no"] = clock_no