From f44ff2bac4c8e84cff6a1303fcaffcce16673d57 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 12 Apr 2023 19:13:14 +0200 Subject: [PATCH] integration/soc/SoCBusHandler: Force interconnect to Crossbar when at least one region has the decoder disabled. See https://github.com/enjoy-digital/litex/issues/1665 since optimizations on Shared Interconnect can't be used with disabled decoder. --- litex/soc/integration/soc.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) mode change 100755 => 100644 litex/soc/integration/soc.py diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py old mode 100755 new mode 100644 index 48dd8226c..b2f9c172c --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -76,7 +76,7 @@ class SoCRegion: self.logger.error("Origin needs to be aligned on size:") self.logger.error(self) raise SoCError() - if not self.decode or (origin == 0) and (size == 2**bus.address_width): + if (not self.decode) or ((origin == 0) and (size == 2**bus.address_width)): return lambda a: True origin >>= int(log2(bus.data_width//8)) # bytes to words aligned. size >>= int(log2(bus.data_width//8)) # bytes to words aligned. @@ -490,6 +490,19 @@ class SoCBusHandler(LiteXModule): slave = next(iter(self.slaves.values()))) # Otherwise, use InterconnectShared/Crossbar. else: + # If one region has the decoder disabled, force interconnect to crossbar since shared + # interconnect relies on the fact that all regions have decoder to optimize logic. + force_crossbar = False + for region in self.regions.values(): + if region.decode == False: + force_crossbar = True + if force_crossbar: + self.logger.info("{} interconnect to {}.".format( + colorer("Forcing"), + colorer("Crossbar"), + )) + self.interconnect = "crossbar" + # Interconnect Logic. interconnect_cls = { "shared" : interconnect_shared_cls, "crossbar": interconnect_crossbar_cls,