diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py
index 0d6401c4b..74585ea46 100644
--- a/litex/soc/cores/video.py
+++ b/litex/soc/cores/video.py
@@ -606,12 +606,15 @@ class VideoTerminal(Module):
 
 class VideoFrameBuffer(Module, AutoCSR):
     """Video FrameBuffer"""
-    def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65536, clock_domain="sys", clock_faster_than_sys=False, depth=32):
+    def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65536, clock_domain="sys", clock_faster_than_sys=False, format="rgb888"):
         self.vtg_sink  = vtg_sink = stream.Endpoint(video_timing_layout)
         self.source    = source   = stream.Endpoint(video_data_layout)
         self.underflow = Signal()
 
-        assert((depth == 32) or (depth == 16))
+        self.depth = depth = {
+            "rgb888" : 32,
+            "rgb565" : 16
+        }[format]
 
         # # #
 
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index d99a526ef..ee3b756b4 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1784,7 +1784,7 @@ class LiteXSoC(SoC):
         self.comb += vt.source.connect(phy if isinstance(phy, stream.Endpoint) else phy.sink)
 
     # Add Video Framebuffer ------------------------------------------------------------------------
-    def add_video_framebuffer(self, name="video_framebuffer", phy=None, timings="800x600@60Hz", clock_domain="sys", depth=32):
+    def add_video_framebuffer(self, name="video_framebuffer", phy=None, timings="800x600@60Hz", clock_domain="sys", format="rgb888"):
         # Imports.
         from litex.soc.cores.video import VideoTimingGenerator, VideoFrameBuffer
 
@@ -1799,12 +1799,12 @@ class LiteXSoC(SoC):
         hres = int(timings.split("@")[0].split("x")[0])
         vres = int(timings.split("@")[0].split("x")[1])
         vfb = VideoFrameBuffer(self.sdram.crossbar.get_port(),
-            hres = hres,
-            vres = vres,
-            base = base,
+            hres   = hres,
+            vres   = vres,
+            base   = base,
+            format = format,
             clock_domain          = clock_domain,
             clock_faster_than_sys = vtg.video_timings["pix_clk"] > self.sys_clk_freq,
-            depth = depth
         )
         setattr(self.submodules, name, vfb)
 
@@ -1818,5 +1818,5 @@ class LiteXSoC(SoC):
         self.add_constant("VIDEO_FRAMEBUFFER_BASE", base)
         self.add_constant("VIDEO_FRAMEBUFFER_HRES", hres)
         self.add_constant("VIDEO_FRAMEBUFFER_VRES", vres)
-        self.add_constant("VIDEO_FRAMEBUFFER_DEPTH", depth)
+        self.add_constant("VIDEO_FRAMEBUFFER_DEPTH", vfb.depth)