diff --git a/litex/build/lattice/trellis.py b/litex/build/lattice/trellis.py
index 0f365c831..367864237 100644
--- a/litex/build/lattice/trellis.py
+++ b/litex/build/lattice/trellis.py
@@ -146,6 +146,10 @@ class LatticeTrellisToolchain(YosysNextPNRToolchain):
     }
 
     def add_period_constraint(self, platform, clk, period):
+        if clk is None:
+            return
+        if hasattr(clk, "p"):
+            clk = clk.p
         platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(
             freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
 
diff --git a/litex/build/microsemi/libero_soc.py b/litex/build/microsemi/libero_soc.py
index 91a0b2bfd..b4ca3cde7 100644
--- a/litex/build/microsemi/libero_soc.py
+++ b/litex/build/microsemi/libero_soc.py
@@ -236,13 +236,6 @@ class MicrosemiLiberoSoCPolarfireToolchain(GenericToolchain):
         if subprocess.call(shell + [script]) != 0:
             raise OSError("Subprocess failed")
 
-    def add_period_constraint(self, platform, clk, period):
-        if clk in self.clocks:
-            if period != self.clocks[clk]:
-                raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
-                    .format(self.clocks[clk], period))
-        self.clocks[clk] = period
-
     def add_false_path_constraint(self, platform, from_, to):
         if (to, from_) not in self.false_paths:
             self.false_paths.add((from_, to))
diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py
index 19ad929ed..ca20f7ad5 100755
--- a/litex/build/xilinx/ise.py
+++ b/litex/build/xilinx/ise.py
@@ -206,6 +206,10 @@ bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit{fail_stmt}
     # them through clock objects like DCM and PLL objects.
 
     def add_period_constraint(self, platform, clk, period):
+        if clk is None:
+            return
+        if hasattr(clk, "p"):
+            clk = clk.p
         clk.attr.add("keep")
         platform.add_platform_command(
             """