From f628ff6b47d90c783c60bbada5abbf7bc0fc6660 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:37:36 +1000 Subject: [PATCH] WB2CSR: Use CSR address_width for the wishbone bus Currently, we create a wishbone interface with the default address width (30 bits) for the bridge. Instead, create an interface that has the same number of address bits as the CSR bus. Signed-off-by: Benjamin Herrenschmidt --- litex/soc/interconnect/wishbone2csr.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/interconnect/wishbone2csr.py b/litex/soc/interconnect/wishbone2csr.py index b9544aad6..c9e307790 100644 --- a/litex/soc/interconnect/wishbone2csr.py +++ b/litex/soc/interconnect/wishbone2csr.py @@ -10,12 +10,12 @@ from litex.soc.interconnect import csr_bus, wishbone class WB2CSR(Module): def __init__(self, bus_wishbone=None, bus_csr=None): - if bus_wishbone is None: - bus_wishbone = wishbone.Interface() - self.wishbone = bus_wishbone if bus_csr is None: bus_csr = csr_bus.Interface() self.csr = bus_csr + if bus_wishbone is None: + bus_wishbone = wishbone.Interface(adr_width=bus_csr.address_width) + self.wishbone = bus_wishbone # # #