diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index a659f7f36..359ed10b6 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -166,8 +166,7 @@ class Arbiter(Module):
         if controllers is not None:
             masters = controllers
 
-        self.submodules.rr = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
-        cycs = Array(m.cyc for m in masters)
+        self.submodules.rr = roundrobin.RoundRobin(len(masters))
 
         # mux master->slave signals
         for name, size, direction in _layout:
@@ -186,8 +185,6 @@ class Arbiter(Module):
                     else:
                         self.comb += dest.eq(source)
 
-        self.comb += self.rr.ce.eq(target.ack | ~cycs[self.rr.grant])
-
         # connect bus requests to round-robin selector
         reqs = [m.cyc for m in masters]
         self.comb += self.rr.request.eq(Cat(*reqs))