From f68fcef90cc90ebfa1c8b8aea6b5831a17841924 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 9 Feb 2013 17:09:29 +0100
Subject: [PATCH] tb: use default runner

---
 tb/asmicon/asmicon.py         | 3 +--
 tb/asmicon/asmicon_wb.py      | 3 +--
 tb/asmicon/bankmachine.py     | 3 +--
 tb/asmicon/refresher.py       | 3 +--
 tb/asmicon/selector.py        | 3 +--
 tb/framebuffer/framebuffer.py | 3 +--
 6 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/tb/asmicon/asmicon.py b/tb/asmicon/asmicon.py
index d004ff681..6daafd91f 100644
--- a/tb/asmicon/asmicon.py
+++ b/tb/asmicon/asmicon.py
@@ -1,7 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon import *
 
@@ -33,7 +32,7 @@ def main():
 	fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \
 		logger.get_fragment() + \
 		Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	sim = Simulator(fragment, TopLevel("my.vcd"))
 	sim.run(700)
 
 main()
diff --git a/tb/asmicon/asmicon_wb.py b/tb/asmicon/asmicon_wb.py
index 28f6dc286..10e56e8a3 100644
--- a/tb/asmicon/asmicon_wb.py
+++ b/tb/asmicon/asmicon_wb.py
@@ -1,7 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bus import wishbone, wishbone2asmi, asmibus
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon import *
 
@@ -41,7 +40,7 @@ def main():
 		conn.get_fragment() + \
 		logger.get_fragment() + \
 		Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	sim = Simulator(fragment, TopLevel("my.vcd"))
 	sim.run()
 
 main()
diff --git a/tb/asmicon/bankmachine.py b/tb/asmicon/bankmachine.py
index 37ef31128..0221fbd67 100644
--- a/tb/asmicon/bankmachine.py
+++ b/tb/asmicon/bankmachine.py
@@ -1,7 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon.bankmachine import *
 
@@ -42,7 +41,7 @@ def main():
 	fragment = hub.get_fragment() + initiator.get_fragment() + \
 		dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \
 		Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	sim = Simulator(fragment, TopLevel("my.vcd"))
 	sim.run()
 
 main()
diff --git a/tb/asmicon/refresher.py b/tb/asmicon/refresher.py
index cbf1d47e7..a044fcb51 100644
--- a/tb/asmicon/refresher.py
+++ b/tb/asmicon/refresher.py
@@ -2,7 +2,6 @@ from random import Random
 
 from migen.fhdl.structure import *
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon.refresher import *
 
@@ -44,7 +43,7 @@ def main():
 	logger = CommandLogger(dut.cmd)
 	granter = Granter(dut.req, dut.ack)
 	fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
-	sim = Simulator(fragment, Runner())
+	sim = Simulator(fragment)
 	sim.run(400)
 
 main()
diff --git a/tb/asmicon/selector.py b/tb/asmicon/selector.py
index 1a7fafde7..3b99774bd 100644
--- a/tb/asmicon/selector.py
+++ b/tb/asmicon/selector.py
@@ -3,7 +3,6 @@ from random import Random
 from migen.fhdl.structure import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
-from migen.sim.icarus import Runner
 
 from milkymist.asmicon.bankmachine import _AddressSlicer, _SimpleSelector
 
@@ -71,7 +70,7 @@ def main():
 	fragment = hub.get_fragment() + sum([i.get_fragment() for i in initiators], Fragment()) + \
 		logger.get_fragment() + selector.get_fragment() + completer.get_fragment() + \
 		Fragment(sim=[end_simulation])
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+	sim = Simulator(fragment, TopLevel("my.vcd"))
 	sim.run()
 
 main()
diff --git a/tb/framebuffer/framebuffer.py b/tb/framebuffer/framebuffer.py
index 27d33a007..76b1f7ac1 100644
--- a/tb/framebuffer/framebuffer.py
+++ b/tb/framebuffer/framebuffer.py
@@ -1,7 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bus import asmibus
 from migen.sim.generic import Simulator
-from migen.sim.icarus import Runner
 
 from milkymist.framebuffer import *
 
@@ -13,7 +12,7 @@ def main():
 	dut = Framebuffer(1, port, True)
 	
 	fragment = hub.get_fragment() + dut.get_fragment()
-	sim = Simulator(fragment, Runner())
+	sim = Simulator(fragment)
 	
 	sim.run(1)
 	def csr_w(addr, d):