From f6da67fb38fb758679cb9292802b5a7f5115f1e7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 20 Jul 2023 10:35:10 +0200 Subject: [PATCH] soc/add_pcie: Add optional data_width parameter. --- CHANGES.md | 1 + litex/soc/integration/soc.py | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/CHANGES.md b/CHANGES.md index 2953cf799..7bdc601d6 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -43,6 +43,7 @@ - liteeth/core/icmp : Added fifo_depth parameter on LiteEthICMPEcho. - gen/fhdl/verilog : Improved signal sort by name instead of duid to improve reproducibility. - litedram/frontend/dma : Added last generation on end of DMA for LiteDRAMDMAReader. + - litepcie/frontend/dma : Added optional integrated data-width converter and data_width parameters to simplify integration/user logic. [> Changed ---------- diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index ed7cd4b5c..f48665b39 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1970,7 +1970,7 @@ class LiteXSoC(SoC): self.sata_phy.crg.cd_sata_rx.clk) # Add PCIe ------------------------------------------------------------------------------------- - def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32, + def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32, data_width=None, with_dma_buffering = True, dma_buffering_depth=1024, with_dma_loopback = True, with_dma_synchronizer = False, @@ -2036,7 +2036,8 @@ class LiteXSoC(SoC): with_synchronizer = with_dma_synchronizer, with_monitor = with_dma_monitor, with_status = with_dma_status, - address_width = address_width + address_width = address_width, + data_width = data_width, ) self.add_module(name=f"{name}_dma{i}", module=dma) self.msis[f"{name.upper()}_DMA{i}_WRITER"] = dma.writer.irq