From f730f1d7ba14484d3738e36d36df2e36ff9d7ff2 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 13 Aug 2020 12:52:05 +0200 Subject: [PATCH] cores/cpu/vexriscv_smp fix argument parsing --- litex/soc/cores/cpu/vexriscv_smp/core.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 2ee26f2fd..4ebe5b322 100644 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -70,10 +70,10 @@ class VexRiscvSMP(CPU): if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False) if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width) if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width) - if(args.icache_width): VexRiscvSMP.dcache_size = int(args.dcache_size) - if(args.icache_width): VexRiscvSMP.icache_size = int(args.icache_size) - if(args.icache_width): VexRiscvSMP.dcache_ways = int(args.dcache_ways) - if(args.icache_width): VexRiscvSMP.icache_ways = int(args.icache_ways) + if(args.dcache_size): VexRiscvSMP.dcache_size = int(args.dcache_size) + if(args.icache_size): VexRiscvSMP.icache_size = int(args.icache_size) + if(args.dcache_ways): VexRiscvSMP.dcache_ways = int(args.dcache_ways) + if(args.icache_ways): VexRiscvSMP.icache_ways = int(args.icache_ways) @property def mem_map(self):