diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 069772ee7..c11dfb16f 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -40,12 +40,13 @@ class S7Clocking(Module, AutoCSR):
             raise ValueError
         self.clkin_freq = freq
 
-    def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2):
+    def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True):
         assert self.nclkouts < self.nclkouts_max
         clkout = Signal()
         self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
         self.nclkouts += 1
-        self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset)
+        if with_reset:
+            self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset)
         if buf is None:
             self.comb += cd.clk.eq(clkout)
         else: