From f7d468dd1c323c797be1ec98422ee65272cc57ff Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 20 Feb 2023 10:27:10 +0100 Subject: [PATCH] cores/cpus: Generate all CPU configs as LiteX configs (for consistency). --- litex/soc/cores/cpu/naxriscv/core.py | 2 +- litex/soc/cores/cpu/rocket/core.py | 2 +- litex/soc/cores/cpu/vexriscv_smp/core.py | 22 +++++++++++----------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index e1f2a040d..90d471790 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -301,7 +301,7 @@ class NaxRiscv(CPU): soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="cached+linker") # Define ISA. - soc.add_constant("CPU_ISA", NaxRiscv.get_arch()) + soc.add_config("CPU_ISA", NaxRiscv.get_arch()) # Add PLIC Bus (AXILite Slave). self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32) diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index c7baa80f7..342dea849 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -367,7 +367,7 @@ class Rocket(CPU): # Define number of CPUs soc.add_config("CPU_COUNT", num_cores) - soc.add_constant("CPU_ISA", self.get_arch(self.variant)) + soc.add_config("CPU_ISA", self.get_arch(self.variant)) def do_finalize(self): assert hasattr(self, "reset_address") diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 5f335a5f3..a938b1fd6 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -401,24 +401,24 @@ class VexRiscvSMP(CPU): # Define number of CPUs soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count) - soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch()) + soc.add_config("CPU_ISA", VexRiscvSMP.get_arch()) # Constants for cache so we can add them in the DTS. if (VexRiscvSMP.dcache_size > 0): - soc.add_constant("cpu_dcache_size", VexRiscvSMP.dcache_size) - soc.add_constant("cpu_dcache_ways", VexRiscvSMP.dcache_ways) - soc.add_constant("cpu_dcache_block_size", 64) # hardwired? + soc.add_config("CPU_DCACHE_SIZE", VexRiscvSMP.dcache_size) + soc.add_config("CPU_DCACHE_WAYS", VexRiscvSMP.dcache_ways) + soc.add_config("CPU_DCACHE_BLOCK_SIZE", 64) # hardwired? if (VexRiscvSMP.icache_size > 0): - soc.add_constant("cpu_icache_size", VexRiscvSMP.icache_size) - soc.add_constant("cpu_icache_ways", VexRiscvSMP.icache_ways) - soc.add_constant("cpu_icache_block_size", 64) # hardwired? + soc.add_config("CPU_ICACHE_SIZE", VexRiscvSMP.icache_size) + soc.add_config("CPU_ICACHE_WAYS", VexRiscvSMP.icache_ways) + soc.add_config("CPU_ICACHE_BLOCK_SIZE", 64) # hardwired? # Constants for TLB so we can add them in the DTS # full associative so only the size is described. if (VexRiscvSMP.dtlb_size > 0): - soc.add_constant("cpu_dtlb_size", VexRiscvSMP.dtlb_size) - soc.add_constant("cpu_dtlb_ways", VexRiscvSMP.dtlb_size) + soc.add_config("CPU_DTLB_SIZE", VexRiscvSMP.dtlb_size) + soc.add_config("CPU_DTLB_WAYS", VexRiscvSMP.dtlb_size) if (VexRiscvSMP.itlb_size > 0): - soc.add_constant("cpu_itlb_size", VexRiscvSMP.itlb_size) - soc.add_constant("cpu_itlb_ways", VexRiscvSMP.itlb_size) + soc.add_config("CPU_ITLB_SIZE", VexRiscvSMP.itlb_size) + soc.add_config("CPU_ITLB_WAYS", VexRiscvSMP.itlb_size) # Add PLIC as Bus Slave self.plicbus = plicbus = wishbone.Interface()