diff --git a/make.py b/make.py
index 401d6a2dd..57f938a37 100644
--- a/make.py
+++ b/make.py
@@ -111,16 +111,11 @@ BIST: {}
 
 	# dependencies
 	if actions["all"]:
-		actions["clean"] = True
 		actions["build-csr-csv"] = True
 		actions["build-bitstream"] = True
 		actions["load-bitstream"] = True
 
-	if actions["build-core"]:
-		actions["clean"] = True
-
 	if actions["build-bitstream"]:
-		actions["clean"] = True
 		actions["build-csr-csv"] = True
 		actions["build-bitstream"] = True
 		actions["load-bitstream"] = True
@@ -146,7 +141,10 @@ BIST: {}
 		tools.write_to_file("build/litesata.v", src)
 
 	if actions["build-bitstream"]:
-		platform.build(soc, build_name=build_name)
+		vns = platform.build(soc, build_name=build_name, run=False)
+		if hasattr(soc, "do_exit") and vns is not None:
+			if hasattr(soc.do_exit, '__call__'):
+				soc.do_exit(vns)
 
 	if actions["load-bitstream"]:
 		prog = platform.create_programmer()
diff --git a/targets/bist.py b/targets/bist.py
index 118d3a1ac..e298e4243 100644
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -1,4 +1,4 @@
-import os, atexit
+import os
 
 from litesata.common import *
 from migen.bank import csrgen
@@ -203,7 +203,6 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
 
 		self.submodules.la = LiteScopeLA(debug, 2048)
 		self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-		atexit.register(self.exit, platform)
 
 	def do_finalize(self):
 		BISTSoC.do_finalize(self)
@@ -216,8 +215,7 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
 			self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state)
 		]
 
-	def exit(self, platform):
-		if platform.vns is not None:
-			self.la.export(platform.vns, "../test/la.csv")
+	def do_exit(self, vns):
+		self.la.export(vns, "test/la.csv")
 
 default_subtarget = BISTSoC