From f823d06cf10b133683d8970e69af1140418802dd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 26 Feb 2013 23:14:09 +0100 Subject: [PATCH] examples: update & simplify --- .../client/{test_MigIo.py => test_MiIo.py} | 27 +++++------- .../client/test_MiLa_0.py} | 43 ++++++++----------- .../client/test_MiLa_1.py} | 43 ++++++++----------- .../client/{test_MigIo.py => test_MiIo.py} | 27 +++++------- .../client/test_MiLa_0.py} | 43 ++++++++----------- .../client/test_MiLa_1.py} | 43 ++++++++----------- 6 files changed, 92 insertions(+), 134 deletions(-) rename examples/de0_nano/client/{test_MigIo.py => test_MiIo.py} (70%) rename examples/{de1/client/test_MigLa_0.py => de0_nano/client/test_MiLa_0.py} (64%) rename examples/{de1/client/test_MigLa_1.py => de0_nano/client/test_MiLa_1.py} (60%) rename examples/de1/client/{test_MigIo.py => test_MiIo.py} (70%) rename examples/{de0_nano/client/test_MigLa_0.py => de1/client/test_MiLa_0.py} (64%) rename examples/{de0_nano/client/test_MigLa_1.py => de1/client/test_MiLa_1.py} (60%) diff --git a/examples/de0_nano/client/test_MigIo.py b/examples/de0_nano/client/test_MiIo.py similarity index 70% rename from examples/de0_nano/client/test_MigIo.py rename to examples/de0_nano/client/test_MiIo.py index 64c8727c2..338e09f2b 100644 --- a/examples/de0_nano/client/test_MigIo.py +++ b/examples/de0_nano/client/test_MiIo.py @@ -1,15 +1,8 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * +from migScope import trigger, recorder, migIo import sys sys.path.append("../../../") -from migScope import trigger, recorder, migIo -import spi2Csr from spi2Csr.tools.uart2Spi import * #============================================================================== @@ -25,17 +18,17 @@ record_size = 1024 csr = Uart2Spi(1,115200) # Csr Addr -MIGIO_ADDR = 0x0000 +MIIO_ADDR = 0x0000 -# MigScope Configuration -# migIo -migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr) +# Miscope Configuration +# miIo +miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr) def led_anim0(): for i in range(10): - migIo0.write(0xA5) + miIo0.write(0xA5) time.sleep(0.1) - migIo0.write(0x5A) + miIo0.write(0x5A) time.sleep(0.1) def led_anim1(): @@ -43,13 +36,13 @@ def led_anim1(): for j in range(4): ledData = 1 for i in range(8): - migIo0.write(ledData) + miIo0.write(ledData) time.sleep(i*i*0.0020) ledData = (ledData<<1) #Led >> ledData = 128 for i in range(8): - migIo0.write(ledData) + miIo0.write(ledData) time.sleep(i*i*0.0020) ledData = (ledData>>1) @@ -64,6 +57,6 @@ led_anim1() time.sleep(1) print("- Read Switch: ",end=' ') -print(migIo0.read()) +print(miIo0.read()) diff --git a/examples/de1/client/test_MigLa_0.py b/examples/de0_nano/client/test_MiLa_0.py similarity index 64% rename from examples/de1/client/test_MigLa_0.py rename to examples/de0_nano/client/test_MiLa_0.py index df8fd7f9e..d687eae8d 100644 --- a/examples/de1/client/test_MigLa_0.py +++ b/examples/de0_nano/client/test_MiLa_0.py @@ -1,17 +1,10 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * +from miscope import trigger, recorder, miIo, miLa +from miscope.tools.truthtable import * +from miscope.tools.vcd import * import sys sys.path.append("../../../") -from migScope import trigger, recorder, migIo, migLa -from migScope.tools.truthtable import * -from migScope.tools.vcd import * -import spi2Csr from spi2Csr.tools.uart2Spi import * #============================================================================== @@ -25,21 +18,21 @@ dat_width = 16 record_size = 4096 # Csr Addr -MIGIO_ADDR = 0x0000 -MIGLA_ADDR = 0x0200 +MIIO_ADDR = 0x0000 +MILA_ADDR = 0x0200 -csr = Uart2Spi(1,115200,debug=False) +csr = Uart2Spi(1, 115200, debug=False) -# MigScope Configuration -# migIo0 -migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr) +# MiScope Configuration +# miIo0 +miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr) -# migIla0 +# miLa0 term0 = trigger.Term(trig_width) trigger0 = trigger.Trigger(trig_width, [term0]) recorder0 = recorder.Recorder(dat_width, record_size) -migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr) +miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr) #============================================================================== # T E S T M I G L A @@ -52,19 +45,19 @@ def capture(size): global recorder0 global dat_vcd sum_tt = gen_truth_table("term0") - migLa0.trig.sum.write(sum_tt) - migLa0.rec.reset() - migLa0.rec.offset(0) - migLa0.rec.arm() + miLa0.trig.sum.write(sum_tt) + miLa0.rec.reset() + miLa0.rec.offset(0) + miLa0.rec.arm() print("-Recorder [Armed]") print("-Waiting Trigger...", end = ' ') - while(not migLa0.rec.is_done()): + while(not miLa0.rec.is_done()): time.sleep(0.1) print("[Done]") print("-Receiving Data...", end = ' ') sys.stdout.flush() - dat_vcd += migLa0.rec.read(size) + dat_vcd += miLa0.rec.read(size) print("[Done]") print("Capturing Ramp..") @@ -87,4 +80,4 @@ capture(1024) myvcd = Vcd() myvcd.add(Var("wire", 16, "trig_dat", dat_vcd)) -myvcd.write("test_MigLa_0.vcd") \ No newline at end of file +myvcd.write("test_MiLa_0.vcd") \ No newline at end of file diff --git a/examples/de1/client/test_MigLa_1.py b/examples/de0_nano/client/test_MiLa_1.py similarity index 60% rename from examples/de1/client/test_MigLa_1.py rename to examples/de0_nano/client/test_MiLa_1.py index 69c8e203c..d5c2bebad 100644 --- a/examples/de1/client/test_MigLa_1.py +++ b/examples/de0_nano/client/test_MiLa_1.py @@ -1,17 +1,10 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * +from miscope import trigger, recorder, miIo, miLa +from miscope.tools.truthtable import * +from miscope.tools.vcd import * import sys sys.path.append("../../../") -from migScope import trigger, recorder, migIo, migLa -from migScope.tools.truthtable import * -from migScope.tools.vcd import * -import spi2Csr from spi2Csr.tools.uart2Spi import * #============================================================================== @@ -25,21 +18,21 @@ dat_width = 32 record_size = 4096 # Csr Addr -MIGIO0_ADDR = 0x0000 -MIGLA1_ADDR = 0x0600 +MIIO0_ADDR = 0x0000 +MILA1_ADDR = 0x0600 -csr = Uart2Spi(1,115200,debug=False) +csr = Uart2Spi(1, 115200, debug=False) -# MigScope Configuration -# migIo0 -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr) +# MiScope Configuration +# miIo0 +miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr) -# migIla1 +# miLa1 term1 = trigger.Term(trig_width) trigger1 = trigger.Trigger(trig_width, [term1]) recorder1 = recorder.Recorder(dat_width, record_size) -migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1, csr) +miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr) #============================================================================== # T E S T M I G L A @@ -49,25 +42,25 @@ recorder1.size(1024) term1.write(0x0100005A,0x0100005A) sum_tt = gen_truth_table("term1") -migLa1.trig.sum.write(sum_tt) -migLa1.rec.reset() -migLa1.rec.offset(256) -migLa1.rec.arm() +miLa1.trig.sum.write(sum_tt) +miLa1.rec.reset() +miLa1.rec.offset(256) +miLa1.rec.arm() print("-Recorder [Armed]") print("-Waiting Trigger...", end = ' ') csr.write(0x0000,0x5A) -while(not migLa1.rec.is_done()): +while(not miLa1.rec.is_done()): time.sleep(0.1) print("[Done]") print("-Receiving Data...", end = ' ') sys.stdout.flush() -dat_vcd += migLa1.rec.read(1024) +dat_vcd += miLa1.rec.read(1024) print("[Done]") myvcd = Vcd() myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8))) myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24))) myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24))) -myvcd.write("test_MigLa_1.vcd") \ No newline at end of file +myvcd.write("test_MiLa_1.vcd") \ No newline at end of file diff --git a/examples/de1/client/test_MigIo.py b/examples/de1/client/test_MiIo.py similarity index 70% rename from examples/de1/client/test_MigIo.py rename to examples/de1/client/test_MiIo.py index 64c8727c2..338e09f2b 100644 --- a/examples/de1/client/test_MigIo.py +++ b/examples/de1/client/test_MiIo.py @@ -1,15 +1,8 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * +from migScope import trigger, recorder, migIo import sys sys.path.append("../../../") -from migScope import trigger, recorder, migIo -import spi2Csr from spi2Csr.tools.uart2Spi import * #============================================================================== @@ -25,17 +18,17 @@ record_size = 1024 csr = Uart2Spi(1,115200) # Csr Addr -MIGIO_ADDR = 0x0000 +MIIO_ADDR = 0x0000 -# MigScope Configuration -# migIo -migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr) +# Miscope Configuration +# miIo +miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr) def led_anim0(): for i in range(10): - migIo0.write(0xA5) + miIo0.write(0xA5) time.sleep(0.1) - migIo0.write(0x5A) + miIo0.write(0x5A) time.sleep(0.1) def led_anim1(): @@ -43,13 +36,13 @@ def led_anim1(): for j in range(4): ledData = 1 for i in range(8): - migIo0.write(ledData) + miIo0.write(ledData) time.sleep(i*i*0.0020) ledData = (ledData<<1) #Led >> ledData = 128 for i in range(8): - migIo0.write(ledData) + miIo0.write(ledData) time.sleep(i*i*0.0020) ledData = (ledData>>1) @@ -64,6 +57,6 @@ led_anim1() time.sleep(1) print("- Read Switch: ",end=' ') -print(migIo0.read()) +print(miIo0.read()) diff --git a/examples/de0_nano/client/test_MigLa_0.py b/examples/de1/client/test_MiLa_0.py similarity index 64% rename from examples/de0_nano/client/test_MigLa_0.py rename to examples/de1/client/test_MiLa_0.py index df8fd7f9e..d687eae8d 100644 --- a/examples/de0_nano/client/test_MigLa_0.py +++ b/examples/de1/client/test_MiLa_0.py @@ -1,17 +1,10 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * +from miscope import trigger, recorder, miIo, miLa +from miscope.tools.truthtable import * +from miscope.tools.vcd import * import sys sys.path.append("../../../") -from migScope import trigger, recorder, migIo, migLa -from migScope.tools.truthtable import * -from migScope.tools.vcd import * -import spi2Csr from spi2Csr.tools.uart2Spi import * #============================================================================== @@ -25,21 +18,21 @@ dat_width = 16 record_size = 4096 # Csr Addr -MIGIO_ADDR = 0x0000 -MIGLA_ADDR = 0x0200 +MIIO_ADDR = 0x0000 +MILA_ADDR = 0x0200 -csr = Uart2Spi(1,115200,debug=False) +csr = Uart2Spi(1, 115200, debug=False) -# MigScope Configuration -# migIo0 -migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr) +# MiScope Configuration +# miIo0 +miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr) -# migIla0 +# miLa0 term0 = trigger.Term(trig_width) trigger0 = trigger.Trigger(trig_width, [term0]) recorder0 = recorder.Recorder(dat_width, record_size) -migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr) +miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr) #============================================================================== # T E S T M I G L A @@ -52,19 +45,19 @@ def capture(size): global recorder0 global dat_vcd sum_tt = gen_truth_table("term0") - migLa0.trig.sum.write(sum_tt) - migLa0.rec.reset() - migLa0.rec.offset(0) - migLa0.rec.arm() + miLa0.trig.sum.write(sum_tt) + miLa0.rec.reset() + miLa0.rec.offset(0) + miLa0.rec.arm() print("-Recorder [Armed]") print("-Waiting Trigger...", end = ' ') - while(not migLa0.rec.is_done()): + while(not miLa0.rec.is_done()): time.sleep(0.1) print("[Done]") print("-Receiving Data...", end = ' ') sys.stdout.flush() - dat_vcd += migLa0.rec.read(size) + dat_vcd += miLa0.rec.read(size) print("[Done]") print("Capturing Ramp..") @@ -87,4 +80,4 @@ capture(1024) myvcd = Vcd() myvcd.add(Var("wire", 16, "trig_dat", dat_vcd)) -myvcd.write("test_MigLa_0.vcd") \ No newline at end of file +myvcd.write("test_MiLa_0.vcd") \ No newline at end of file diff --git a/examples/de0_nano/client/test_MigLa_1.py b/examples/de1/client/test_MiLa_1.py similarity index 60% rename from examples/de0_nano/client/test_MigLa_1.py rename to examples/de1/client/test_MiLa_1.py index 69c8e203c..d5c2bebad 100644 --- a/examples/de0_nano/client/test_MigLa_1.py +++ b/examples/de1/client/test_MiLa_1.py @@ -1,17 +1,10 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * +from miscope import trigger, recorder, miIo, miLa +from miscope.tools.truthtable import * +from miscope.tools.vcd import * import sys sys.path.append("../../../") -from migScope import trigger, recorder, migIo, migLa -from migScope.tools.truthtable import * -from migScope.tools.vcd import * -import spi2Csr from spi2Csr.tools.uart2Spi import * #============================================================================== @@ -25,21 +18,21 @@ dat_width = 32 record_size = 4096 # Csr Addr -MIGIO0_ADDR = 0x0000 -MIGLA1_ADDR = 0x0600 +MIIO0_ADDR = 0x0000 +MILA1_ADDR = 0x0600 -csr = Uart2Spi(1,115200,debug=False) +csr = Uart2Spi(1, 115200, debug=False) -# MigScope Configuration -# migIo0 -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr) +# MiScope Configuration +# miIo0 +miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr) -# migIla1 +# miLa1 term1 = trigger.Term(trig_width) trigger1 = trigger.Trigger(trig_width, [term1]) recorder1 = recorder.Recorder(dat_width, record_size) -migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1, csr) +miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr) #============================================================================== # T E S T M I G L A @@ -49,25 +42,25 @@ recorder1.size(1024) term1.write(0x0100005A,0x0100005A) sum_tt = gen_truth_table("term1") -migLa1.trig.sum.write(sum_tt) -migLa1.rec.reset() -migLa1.rec.offset(256) -migLa1.rec.arm() +miLa1.trig.sum.write(sum_tt) +miLa1.rec.reset() +miLa1.rec.offset(256) +miLa1.rec.arm() print("-Recorder [Armed]") print("-Waiting Trigger...", end = ' ') csr.write(0x0000,0x5A) -while(not migLa1.rec.is_done()): +while(not miLa1.rec.is_done()): time.sleep(0.1) print("[Done]") print("-Receiving Data...", end = ' ') sys.stdout.flush() -dat_vcd += migLa1.rec.read(1024) +dat_vcd += miLa1.rec.read(1024) print("[Done]") myvcd = Vcd() myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8))) myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24))) myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24))) -myvcd.write("test_MigLa_1.vcd") \ No newline at end of file +myvcd.write("test_MiLa_1.vcd") \ No newline at end of file