From f89e883ab099908cdaaf97b2d0494cc4f5937e2b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 11 Nov 2021 11:44:15 +0100 Subject: [PATCH] soc/cores/clock/efinix_trion: Add clock constraints to PLL's clkouts. --- litex/soc/cores/clock/efinix_trion.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/clock/efinix_trion.py b/litex/soc/cores/clock/efinix_trion.py index 38c6303fc..e97294d53 100644 --- a/litex/soc/cores/clock/efinix_trion.py +++ b/litex/soc/cores/clock/efinix_trion.py @@ -51,7 +51,6 @@ class TRIONPLL(Module): pin_name = self.platform.parser.get_gpio_instance_from_pin(pad_name) if pin_name.count("_") == 2: pin_name = pin_name.rsplit("_", 1)[0] - self.platform.toolchain.excluded_ios.append(clkin) #tpl = "create_clock -name {clk} -period {period} [get_ports {{{clk}}}]" @@ -83,7 +82,8 @@ class TRIONPLL(Module): def create_clkout(self, cd, freq, phase=0, margin=1e-2, name="", with_reset=False): assert self.nclkouts < self.nclkouts_max - clk_out_name = "{}_CLKOUT{}".format(self.name, self.nclkouts) if name == "" else name + clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name + self.platform.toolchain.additional_sdc_commands.append(f"create_clock -period {1e9/freq} {clk_out_name}") if cd is not None: self.platform.add_extension([(clk_out_name, 0, Pins(1))])