From f8acc5f50644c5bd9f627714ac97fb00db502354 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Tue, 25 Jan 2022 21:44:02 +0100
Subject: [PATCH] litex/soc/cores/clock/xilinx_common: fix yosys synth: replace
 FD by FDCE

---
 litex/soc/cores/clock/xilinx_common.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/clock/xilinx_common.py b/litex/soc/cores/clock/xilinx_common.py
index fdccb7864..02b9d9f46 100644
--- a/litex/soc/cores/clock/xilinx_common.py
+++ b/litex/soc/cores/clock/xilinx_common.py
@@ -145,7 +145,7 @@ class XilinxClocking(Module, AutoCSR):
     def add_reset_delay(self, cycles):
         for i in range(cycles):
             reset = Signal()
-            self.specials += Instance("FD", i_C=self.clkin, i_D=self.reset, o_Q=reset)
+            self.specials += Instance("FDCE", i_C=self.clkin, i_CE=1, i_CLR=0, i_D=self.reset, o_Q=reset)
             self.reset = reset
 
     def do_finalize(self):