From 07e11858c61609b66357dfdaa9359a20faf5d958 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 24 Aug 2024 12:19:34 +0200 Subject: [PATCH 1/2] soc/cores/clock/colognechip.py: rework/fix locked signal --- litex/soc/cores/clock/colognechip.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/clock/colognechip.py b/litex/soc/cores/clock/colognechip.py index 5f1d9f151..e331fa8ef 100644 --- a/litex/soc/cores/clock/colognechip.py +++ b/litex/soc/cores/clock/colognechip.py @@ -130,6 +130,8 @@ class GateMatePLL(LiteXModule): freqInMHz = self._clkin_freq/1e6 freqOutMHz = clkout_freq/1e6 + locked_s1 = Signal() + self.specials += Instance("CC_PLL", p_REF_CLK = str(freqInMHz), # reference input in MHz p_OUT_CLK = str(freqOutMHz), # pll output frequency in MHz @@ -141,11 +143,12 @@ class GateMatePLL(LiteXModule): i_CLK_REF = self._clkin if not self._usr_clk_ref else Open(), i_USR_CLK_REF = self._clkin if self._usr_clk_ref else Open(), i_CLK_FEEDBACK = 0, - i_USR_LOCKED_STDY_RST = self.reset, + i_USR_LOCKED_STDY_RST = 0, o_CLK_REF_OUT = Open(), - o_USR_PLL_LOCKED_STDY = self.locked, - o_USR_PLL_LOCKED = Open(), + o_USR_PLL_LOCKED_STDY = Open(), + o_USR_PLL_LOCKED = locked_s1, **{f"o_CLK{p}" : c for (p, (c, _)) in self._clkouts.items()}, **{f"p_CLK{p}_DOUB" : v for (p, v) in clk_doub.items()}, ) + self.comb += self.locked.eq(locked_s1 & ~self.reset) From 0fcc27f58f18756bf8f1d1b355b938578f346e26 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 24 Aug 2024 12:20:19 +0200 Subject: [PATCH 2/2] build/colognechip/colognechip.py: simplify constrains file with the new toolchain --- litex/build/colognechip/colognechip.py | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/litex/build/colognechip/colognechip.py b/litex/build/colognechip/colognechip.py index 5ae48da0a..bd44e6324 100644 --- a/litex/build/colognechip/colognechip.py +++ b/litex/build/colognechip/colognechip.py @@ -44,18 +44,6 @@ class CologneChipToolchain(GenericToolchain): # IO Constraints (.ccf) ------------------------------------------------------------------------ - def _get_pin_direction(self, pinname): - pins = self.platform.constraint_manager.get_io_signals() - for pin in sorted(pins, key=lambda x: x.duid): - if (pinname.split("[")[0] == pin.name): - if pin.direction == "output": - return "Pin_out" - elif pin.direction == "input": - return "Pin_in" - else: - return "Pin_inout" - return "Unknown" - def build_io_constraints(self): ccf = [] @@ -70,8 +58,7 @@ class CologneChipToolchain(GenericToolchain): for name, pin, other in flat_sc: pin_cst = "" if pin != "X": - direction = self._get_pin_direction(name) - pin_cst = f"{direction} \"{name}\" Loc = \"{pin}\"" + pin_cst = f"Net \"{name}\" Loc = \"{pin}\"" for c in other: if isinstance(c, Misc):