From fa22d6aa82ee145671a424c7b3112daa82c9ca0d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 10 Jan 2020 12:52:14 +0100
Subject: [PATCH] wishbone/Cache: avoid REFILL_WRTAG state to improve speed.

---
 litex/soc/interconnect/wishbone.py | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 1fbdf9759..d9cdcd3a6 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -606,7 +606,10 @@ class Cache(Module):
                 If(tag_do.dirty,
                     NextState("EVICT")
                 ).Else(
-                    NextState("REFILL_WRTAG")
+                    # Write the tag first to set the slave address
+                    tag_port.we.eq(1),
+                    word_clr.eq(1),
+                    NextState("REFILL")
                 )
             )
         )
@@ -618,16 +621,13 @@ class Cache(Module):
             If(slave.ack,
                 word_inc.eq(1),
                  If(word_is_last(word),
-                    NextState("REFILL_WRTAG")
+                    # Write the tag first to set the slave address
+                    tag_port.we.eq(1),
+                    word_clr.eq(1),
+                    NextState("REFILL")
                 )
             )
         )
-        fsm.act("REFILL_WRTAG",
-            # Write the tag first to set the slave address
-            tag_port.we.eq(1),
-            word_clr.eq(1),
-            NextState("REFILL")
-        )
         fsm.act("REFILL",
             slave.stb.eq(1),
             slave.cyc.eq(1),