From fa260f5b425b83afa08264fc8dee0feba2a32921 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 9 Dec 2018 09:45:17 +0100 Subject: [PATCH] gen/fhdl: add simulation Display, Finish support. In some simulation cases, it's easier to add debug traces directly in the code than in the verilog/Migen testbench. This adds support for verilog $display in Migen code. Being able to terminate a simulation from the code is also useful, this also add support for verilog $finish. --- litex/gen/fhdl/verilog.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index 9f3d1b672..773c763f1 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -155,6 +155,17 @@ def _printnode(ns, at, level, node, target_filter=None): return r else: return "" + elif isinstance(node, Display): + s = "\"" + node.s + "\"" + for arg in node.args: + s += ", " + if isinstance(arg, Signal): + s += ns.get_name(arg) + else: + s += str(arg) + return "\t"*level + "$display(" + s + ");\n" + elif isinstance(node, Finish): + return "\t"*level + "$finish;\n" else: raise TypeError("Node of unrecognized type: "+str(type(node)))