From fa629b782f5dbfb857e430baca715446acb14542 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Oct 2023 11:40:31 +0200 Subject: [PATCH] CHANGES: Update. --- CHANGES.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGES.md b/CHANGES.md index 035510b3d..4d795a814 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -4,6 +4,7 @@ -------- - liteeth/arp : Fixed response on table update. - litesata/us(p)sataphy : Fixed data_width=32 case. + - clock/lattice_ecp5 : Fixed phase calculation. [> Added -------- @@ -18,6 +19,7 @@ - soc/cores : Added Ti60F100 HyperRAM support. - build/xilinx : Added initial OpenXC7 support (and improved Yosys-NextPnr). - build/efinix : Added JTAG-UART/JTAGBone support. + - interconnect/wishbone : Added byte/word addressing support. [> Changed ----------