From faae1ea95aa9bc750d498cd02f2bddf18756675f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 13 Dec 2023 09:24:23 +0100 Subject: [PATCH] integration/soc/jtag: Switch JTAGPHY to sys_clk/simplify. --- litex/soc/integration/soc.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 91b3b0931..17fe98f79 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1440,10 +1440,7 @@ class LiteXSoC(SoC): # JTAG UART. elif uart_name in ["jtag_uart"]: from litex.soc.cores.jtag import JTAGPHY - # Run JTAG-UART in sys_jtag clk domain similar to sys clk domain but without sys_rst. - self.cd_sys_jtag = ClockDomain() - self.comb += self.cd_sys_jtag.clk.eq(ClockSignal("sys")) - uart_phy = JTAGPHY(device=self.platform.device, clock_domain="sys_jtag", platform=self.platform) + uart_phy = JTAGPHY(device=self.platform.device, platform=self.platform) uart = UART(uart_phy, **uart_kwargs) # Sim.