diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index 6480e4773..64e0ffae5 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -60,9 +60,7 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u
 #endif
 	flush_cpu_icache();
 	flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
-#endif
 
 #if defined(CONFIG_CPU_TYPE_MOR1KX) && defined(CONFIG_CPU_VARIANT_LINUX)
 	/* Mainline Linux expects to have exception vector base address set to the
diff --git a/litex/soc/software/libbase/memtest.c b/litex/soc/software/libbase/memtest.c
index 09e15bf53..779858a3c 100644
--- a/litex/soc/software/libbase/memtest.c
+++ b/litex/soc/software/libbase/memtest.c
@@ -7,9 +7,9 @@
 #include <generated/soc.h>
 #include <generated/csr.h>
 
-// #define MEMTEST_BUS_DEBUG
-// #define MEMTEST_DATA_DEBUG
-// #define MEMTEST_ADDR_DEBUG
+//#define MEMTEST_BUS_DEBUG
+//#define MEMTEST_DATA_DEBUG
+//#define MEMTEST_ADDR_DEBUG
 
 #define KIB 1024
 #define MIB (KIB*1024)
@@ -54,9 +54,7 @@ int memtest_bus(unsigned int *addr, unsigned long size)
 
 	/* Flush caches */
 	flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
-#endif
 
 	/* Read/Verify One/Zero pattern */
 	for(i=0; i<size/4; i++) {
@@ -76,9 +74,7 @@ int memtest_bus(unsigned int *addr, unsigned long size)
 
 	/* Flush caches */
 	flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
-#endif
 
 	/* Read/Verify One/Zero pattern */
 	for(i = 0; i < size/4; i++) {
@@ -112,9 +108,7 @@ int memtest_addr(unsigned int *addr, unsigned long size, int random)
 
 	/* Flush caches */
 	flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
-#endif
 
 	/* Read/Verify datas */
 	seed_16 = 1;
@@ -177,9 +171,7 @@ int memtest_data(unsigned int *addr, unsigned long size, int random)
 
 	/* Flush caches */
 	flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
-#endif
 
 	/* Read/Verify datas */
 	seed_32 = 1;
@@ -240,9 +232,7 @@ void memspeed(unsigned int *addr, unsigned long size, bool read_only)
 
 	/* flush caches */
 	flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
-#endif
 
 	/* Measure Read speed */
 	timer0_en_write(1);
diff --git a/litex/soc/software/libbase/system.c b/litex/soc/software/libbase/system.c
index 4e5318323..e42589a0a 100644
--- a/litex/soc/software/libbase/system.c
+++ b/litex/soc/software/libbase/system.c
@@ -5,15 +5,15 @@
 #include <generated/mem.h>
 #include <generated/csr.h>
 
-#ifdef CONFIG_L2_SIZE
 void flush_l2_cache(void)
 {
+#ifdef CONFIG_L2_SIZE
 	unsigned int i;
 	for(i=0;i<2*CONFIG_L2_SIZE/4;i++) {
 		((volatile unsigned int *) MAIN_RAM_BASE)[i];
 	}
-}
 #endif
+}
 
 void busy_wait(unsigned int ms)
 {
diff --git a/litex/soc/software/liblitesata/sata.c b/litex/soc/software/liblitesata/sata.c
index e70a613bf..3e8250373 100644
--- a/litex/soc/software/liblitesata/sata.c
+++ b/litex/soc/software/liblitesata/sata.c
@@ -62,12 +62,10 @@ void sata_read(uint32_t sector, uint32_t count, uint8_t* buf)
 	}
 
 #ifndef CONFIG_CPU_HAS_DMA_BUS
-	/* Flush CPU caches */
+	/* Flush caches */
 	flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
 #endif
-#endif
 }
 
 #endif
diff --git a/litex/soc/software/liblitesdcard/sdcard.c b/litex/soc/software/liblitesdcard/sdcard.c
index 467ee4dc7..78481553e 100644
--- a/litex/soc/software/liblitesdcard/sdcard.c
+++ b/litex/soc/software/liblitesdcard/sdcard.c
@@ -488,12 +488,10 @@ void sdcard_read(uint32_t block, uint32_t count, uint8_t* buf)
 	sdcard_stop_transmission();
 
 #ifndef CONFIG_CPU_HAS_DMA_BUS
-	/* Flush CPU caches */
+	/* Flush caches */
 	flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
 #endif
-#endif
 }
 
 #endif