From fb24ac0ecc158bd1f7b69649bfafc356a709e5a3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 6 Sep 2018 16:40:30 +0200 Subject: [PATCH] cpu/minerva: add workaround on import until code is released --- litex/soc/cores/cpu/minerva/core.py | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 787c91ece..8ae8623bb 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -4,8 +4,6 @@ from migen import * from litex.soc.interconnect import wishbone -from minerva.core import Minerva as MinervaCPU - class Minerva(Module): def __init__(self, platform, cpu_reset_address, variant=None): @@ -17,10 +15,15 @@ class Minerva(Module): ### - self.submodules.cpu = MinervaCPU(reset_address=cpu_reset_address) - self.comb += [ - self.cpu.reset.eq(self.reset), - self.cpu.external_interrupt.eq(self.interrupt), - self.cpu.ibus.connect(self.ibus), - self.cpu.dbus.connect(self.dbus) - ] + try: # FIXME: workaround until Minerva code is released + from minerva.core import Minerva as MinervaCPU + self.submodules.cpu = MinervaCPU(reset_address=cpu_reset_address) + self.comb += [ + self.cpu.reset.eq(self.reset), + self.cpu.external_interrupt.eq(self.interrupt), + self.cpu.ibus.connect(self.ibus), + self.cpu.dbus.connect(self.dbus) + ] + except: + pass +